本論文主要分成兩個部分，第一部分是使用隱蔽式共模共振技術之壓控振盪器設計，第二部分是結合第一部分壓控振盪器電路的4.8 GHz雙迴路鎖相迴路設計。本論文中所設計之電路皆是使用TSMC 0.18 μm 1P6M製程實現，並以on-wafer方式完成量測。
在第一部分中透過變壓器來實現差動模式以及共模模式下共振達到降低相位雜訊之功效。在傳統nMOS-only的交叉耦合對壓控振盪器架構中，二次諧波電流會注入共振腔之電容路徑，此路徑為會讓振盪器波型出現非對稱性，進而讓低頻閃爍雜訊上混頻至振盪頻率去惡化相位雜訊，因此為了讓二次諧波電流不要影響主要振盪波型，我透過共振兩倍頻的方式去讓二倍頻電流路徑形成電阻性，一般而言若只使用電感來實現會需要一顆以上電感才能達成，若是使用變壓器實現就可以在節省面積情況下也能達到共振效果。而在變壓器半徑設計為120 μm、線寬為34 μm、間格為20 μm的情況下，4.8 GHz單邊的電感值為0.558 nH、品質因子為11.71、耦合係數為0.336，兩邊比值為1:1。壓控振盪器量測結果顯示，頻率可調範圍為13.2%，整體頻率從4.6-GHz至5.25 GHz。核心功率消耗為2.88 mW，相位雜訊在1 MHz offset下最佳為-112dBc/Hz，整體輸出功率皆大於-3.2 dBm，晶片面積為0.56 mm^2。
第二部分之4.8 GHz雙迴路鎖相迴路設計先從基本架構做介紹，提到了雙迴路架構相較於傳統單迴路鎖相迴路所帶來的好處，其中包括更寬鬆的設計參數，從零點位置推導證實了此架構節省了非常多的電容面積。由於開迴路增益個別分開的特性，再加上頻寬由比例路徑主導，當頻率在追蹤時積分路徑壓控靈敏度隨著控制電壓改變就不會嚴重影響頻寬，進而保證系統穩定度能夠維持一致。雙迴路的架構之中會刻意把比例路徑的充電泵電流值提高，除了可以更節省電容面積外也可以讓頻率在零點以及頻寬之間的雜訊得到抑制，然而傳統雙迴路的架構通常在比例路徑是直接使用偏壓電阻並聯電容來實現，電阻的使用加上較大的充電泵電流會加速惡化因為非理想效應所帶來的電壓擾動進而影響參考突波和雜訊表現，因此本論文為解決此問題在比例路徑指使用單一充電路徑，也就是只使用單一訊號做控制，並搭配一些開關以及生成開關控制訊號之電路來達到原本相位追蹤的功用，進而大幅改善參考突波表現。由於只使用單一訊號對比例路徑充電泵做控制，因此需要稍微改變相位頻率偵測器的轉移曲線使今天即使有靜態相位誤差使鎖定時參考訊號落後的情況下，比例路徑的充電泵也能維持線性增益，因而維持穩定度。本電路之量測參考頻率設置為100 MHz，除數為48，因此輸出頻率為4.8 GHz。相位雜訊在1 MHz offset下為-91.75dBc/Hz，時脈抖動從10 kHz積分到10 MHz為10.97 ps，輸出功率為-9.38 dBm，參考突波為-54.04 dBc，整體包含輸出緩衝器之功率消耗為9.61 mW。當參考頻率設置為97.9167 MHz，除數為48，因此輸出頻率為4.7 GHz。相位雜訊在1 MHz offset下為-99.75 dBc/Hz，時脈抖動從10 kHz積分到10 MHz為1.87 ps，輸出功率為-2.9 dBm，參考突波為-56.89dBc，提高輸出緩衝器供電後整體之功率消耗為14.96 mW。

The thesis is mainly divided into two parts. The first part focuses on the design of a voltage-controlled oscillator (VCO) using a implicit common-mode resonance technique. The second part presents the design of a 4.8 GHz dual path phase locked loop (PLL) that incorporates the VCO developed in the first part. All circuits designed in this thesis are implemented using the TSMC 0.18 µm 1P6M CMOS process .Both circuits are measured using on wafer measurement approach.
In the first part, a transformer is employed to realize resonance under both differential-mode and common-mode, thereby achieving phase noise reduction. In a conventional nMOS-only cross coupled VCO topology, the second harmonic current is injected into the capacitive path of the resonator. This path introduces waveform asymmetry, causing low frequency flicker noise to up convert to the oscillation frequency and degrade the phase noise. To prevent the second harmonic current from affecting the main oscillation waveform, a common mode resonant technique is utilized to make the second harmonic current path appear resistive. Typically, implementing such resonance with inductors requires more than one inductors; however, using a transformer achieves the same resonant effect while saving chip area.
With a transformer designed using a 120 µm outer radius, 34 µm metal width, and 20 µm spacing. The measurement result of single ended inductance at 4.8 GHz is 0.558 nH, quality factor is 11.71, coupling coefficient is 0.336. Transformer is designed with a 1:1 turns ratio. Measurement results of the VCO show a tuning range of 13.2%, with the oscillation frequency spanning from 4.6 GHz to 5.25 GHz. The core power consumption is 2.88 mW, and the best phase noise performance is −112 dBc/Hz at a 1 MHz offset. The output power remains higher than −3.2 dBm across the entire tuning range, and the overall chip area is 0.56 mm².
In the second part, the design of the 4.8 GHz dual path phase locked loop is introduced starting from its fundamental architecture and its advantage. The advantages of the dual path structure compared with a conventional single path PLL are discussed, including more relaxed design parameters. By deriving the zero frequency location, it is shown that this architecture significantly reduces the required capacitor area. Because the open loop gains of the two paths are separated and the bandwidth is dominated by the proportional path, variations in the VCO gain of the integral path during frequency tracking do not strongly affect the loop bandwidth. As a result, the overall loop stability can be consistently maintained. In a dual path architecture, the charge pump current in the proportional path is intentionally increased. This not only further reduces the required capacitor area but also suppresses noise between the zero frequency and the loop bandwidth. However, in conventional dual path designs, the proportional path is typically implemented using a bias resistor in parallel with a capacitor. The use of a resistor, combined with a larger charge pump current, aggravates voltage disturbances caused by non idealities, which in turn degrade reference spurs and noise performance. To solve this issue, the proposed design uses only a single charge pump control path in the proportional branch—meaning that only a single control signal is used—along with additional switches and circuits that generate the corresponding switch control signals to achieve phase tracking functionality. This approach greatly improves reference spur performance. Because only a single control signal is used to drive the charge pump in the proportional path, the transfer characteristic of the phase–frequency detector (PFD) must be slightly modified. This ensures that even when a static phase error causes the reference signal to lag during lock, the charge pump in the proportional path can still maintain linear gain, thereby preserving loop stability.
In the measurement results, the reference frequency is set to 100 MHz with a divide by 48 ratio, yielding a 4.8 GHz output frequency. The measured phase noise is −91.75 dBc/Hz at a 1 MHz offset, and the integrated jitter from 10 kHz to 10 MHz is 10.97 ps. The output power is −9.38 dBm, and the reference spur is −54.04 dBc. The total power consumption, including the output buffer, is 9.61 mW. When the reference frequency is set to 97.9167 MHz with the same divide by 48 ratio, the output frequency becomes 4.7 GHz. The phase noise improves to −99.75 dBc/Hz at a 1 MHz offset, and the integrated jitter from 10 kHz to 10 MHz is 1.87 ps. The output power is −2.9 dBm, and the reference spur reaches −56.89 dBc. After increasing the output buffer supply voltage, the total power consumption is 14.96 mW and the overall chip area is 0.903 mm².

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