本論文提出基於層轉移技術(layer transfer)的方式垂直堆疊通道，利用鍵結氧化物(bonding oxide)於低溫下實現超過90%的高轉移率，藉此實現疊層互補式場效電晶體(Complementary Field Effect Transistor，CFET)結構。由於層轉移技術僅需使用320度之鍵結後退火(Post Bonding Anneal，PBA)，可大幅降低元件製造的熱預算，並且可保留結構本身之結晶性，使得單晶鍺等高載子遷移率之通道可以應用於此結構之上，形成鍺/矽之異質通道。
本論文旨在實現CFET反相器結構，此反相器結構最大的特點是利用Gate-All-Around (GAA) 結構的垂直堆疊技術，將NMOS與PMOS立體堆疊，並且採用共閘極(common gate)，與傳統CMOS反相器相比之下能夠節省50%的佔地面積，能夠在不微縮元件尺寸的前提下，提升單位面積內能夠佈局的電晶體數量，使晶片效能達到更高效。採用GAA結構可使元件在降低短通道效應(short channel effect，SCE)的同時，單一電晶體之漏電特性將會更低。採用p型鍺/n型矽異質通道之CFET可充分利用高載子遷移率的優勢，對於電壓傳輸特性(Voltage Transfer Characteristic，VTC)有較大的提升。
在製程細節中，我們發現了舊有製程會導致閘極與源極、漏極之間產生漏電流甚至短路，在優化部分製程順序後，將金屬側壁未被蝕刻乾淨的機會降到最低，在後續的量測中發現優化後的製程順序的確改善上述非理想狀況，成功驗證此新製程順序的可行性。另外，在通道釋放的濕蝕刻過程中常常會發生上層通道塌陷，使N、PFET互相短路，影響元件良率，為了避免這種情況，我們使用不同的溶液濃度搭配不同的蝕刻時間來測試蝕刻率，以找到此蝕刻製程的最佳解，從後續的SEM橫切面圖可以驗證我們成功找到此系列蝕刻製程的最佳方法。
在後續的量測中，量測出不錯的元件特性，NFET與PFET的電流開關比接近六個數量級。歸功於Gate-All-Around結構，PFET的S.S.值都有效壓在80mV/dec以下，在較短通道元件中也有78mV/dec，量測出的最低值則是接近理想的70.5 mV/dec。NFET的部分則能夠壓在90 mV/dec以下。

This paper proposes a vertical stacking of channels based on layer transfer technology, using bonding oxide to achieve a high transfer rate of more than 90% at low temperature, thereby realizing a stacked complementary field effect transistor (CFET) structure. Since the layer transfer technology only needs a Post Bonding Anneal (PBA) of 320 degrees, the thermal budget of device manufacturing can be greatly reduced. The crystallinity of the structure can be preserved, making the single crystal Ge and the other high carrier mobility channels can be applied over this structure to form Ge/Si hetero channels.
This paper aims to realize the CFET inverter structure. The biggest feature of this inverter structure is using the vertical stacking technology of the Gate-All-Around (GAA) structure to stack NMOS and PMOS with a common gate structure. Compared with traditional CMOS inverters, can save 50% of the circuit area and increase the number of transistors that can be laid out per unit area without reducing the size of the transistors, making the chip performance more efficient. Using the GAA structure can reduce the device's short channel effect (SCE), and the leakage characteristics of a single transistor will be lower at the same time. CFETs using p-type Ge/n-type Si hetero-channels can take advantage of high carrier mobility and greatly improve the voltage transfer characteristics (VTC).
In the process details, we found that the past process flow would lead to leakage current or even a short circuit between the gate, source, and drain. After optimizing part of the process sequence, it is found in the subsequent measurement that the optimized process sequence does improve the above-mentioned non-ideal situation, and the feasibility of the new process sequence is successfully verified. In addition, the upper channel collapse often during the wet etching process of channel release, which shorts the N and PFETs to each other and affects the component yield. To avoid this situation, we use different solutions with different concentrations, and etching times to test the etching rate to find the best solution for this etching process. From the subsequent SEM cross-sectional view, it can be verified that we have successfully found the best method for this series of etching processes.
In the electrical measurement, good device characteristics were measured, the drain current on/off ratio of NFET and PFET both approaching six orders. Thanks to the Gate-All-Around structure, S.S. values are effectively below 80mV/dec, and 78mV/dec in a shorter channel device. The lowest measured value is 70.5 mV/dec which is close to the ideal value. The NFET S.S. values can be pressed below 90 mV/dec.

[1] IEEE IRDSTM 2021.
[2] C. Auth et al., “A 10nm high performance and low-power CMOS technology featuring 3rd-generation finFET transistors, selfaligned quad patterning, contact overactive gate and Cobalt local interconnects”, IEDM, Session 2.9, December 2017.
[3] G. Yeap, et al., “5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 um2 SRAM cells for mobile SoC and high-performance computing applications”, IEDM, Section 36.7, December 2019.
[4] H. Mertens et al., “Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Dual Work Function Metal Gates”, IEDM, p.19-7, 2016.
[5] I. Lauer et al., “Si Nanowire CMOS Fabricated with Minimal Deviation from RMG FinFET Technology Showing Record Performance”, VLSI, p.140-141, 2015.
[6] Ryckaert J et al., “The Complementary FET (CFET) for CMOS scaling beyond N3”, Symp. VLSI Tech., 141-142, 2018.
[7] E. Capogreco et al., “High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-30nm LG”, Symp. VLSI Tech., T94, 2019.
[8] N. Loubet et al., “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET”, Symp. VLSI Tech., T230-T231, 2017.
[9] L. Chang, M. Ieong, and M. Yang, “CMOS circuit performance enhancement by surface orientation optimization,” IEEE Transactions on Electron Devices, 51(10), pp. 1621-1627. 2004.
[10] TSMC Design Considerations for Gate-All-Around (GAA) Technology.
[11] L. Brunet et al., “First demonstration of a CMOS over CMOS 3D VLSI CoolCubeTM integration on 300mm wafers”, Symp. VLSI Tech., 2016.
[12] VLSI Symposium 2020 – Imec Monolithic CFET
[13] S. Subramanian et al., “First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers”, Symp. VLSI Tech., 2020.
[14] T. Plach, K. Hingerl, S. Tollabimazraehno, G. Hesser, V. Dragoi, and M. Wimplinger, “Mechanisms for room temperature direct wafer bonding,” Journal of Applied Physics, vol. 113, no. 9, p. 094905, 2013.
[15] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, “Nanowire transistors without junctions”, Nature Nanotechnology, Vol. 28, pp. 225 - 229, 2010.
[16] Colinge JP, Lee CW, Akhavan ND, Yan R, Ferain I, Razavi P, Kranti A, Yu R. Junctionless transistors physics and properties. Semiconductor on Insulator Materials for Nanoelectronics Applications and Engineering Materials, DOI: http://dx.doi.org/10.1007/978-3-642-15868-1_10,Spinger-Verlag Berlin Heidelberg 2011.
[17] T.-Z. Hong et al.,” First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)”, IEDM, p.15.5.1-15.5.4, 2020.
[18] 林冠宇、張家豪、沈家志、劉志宏，"電漿深蝕刻設備及其製程技術"，機械工業雜誌，2018年9月號426期。
[19] A. Abedin, A. Asadollahi, K. Garidis, P.-E. Hellström, and M. Ostling, “Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density,” ECS Trans., vol. 75, no. 8, pp. 615–621, 2016.
[20] Murad, SN Ali, et al. "Optimisation and scaling of interfacial GeO2 layers for high-κ gate stacks on germanium and extraction of dielectric constant of GeO2." Solid-state electronics 78 (2012): 136-140.
[21] Castillo-Saenz, Jhonathan, et al. "Properties of Al2O3 Thin Films Grown by PE-ALD at Low Temperature Using H2O and O2 Plasma Oxidants." Coatings 11.10 (2021): 1266.
[22] Mengnan Ke, Mitsuru Takenaka, and Shinichi Takagi. "Impact of Atomic Layer Deposition High k Films on Slow Trap Density in Ge MOS Interfaces With GeOx Interfacial Layers Formed by Plasma Pre-Oxidation", journal of the electron devices society, vol 6, pp. 950–955, 2018.