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研究生：	蕭百宏 Xiao, Bai-Hong
論文名稱：	一正交分頻多工系統之分析與硬體研製 Analysis and Hardware Implementation of An OFDM System
指導教授：	廖德祿 Liao, Teh-Lu
學位類別：	碩士 Master
系所名稱：	工學院 - 工程科學系 Department of Engineering Science
論文出版年：	2003
畢業學年度：	91
語文別：	英文
論文頁數：	77
中文關鍵詞：	正交分頻多工
外文關鍵詞：	FPGA, FFT, OFDM
相關次數：	點閱：99 下載：3
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正交分頻多工(OFDM)傳輸技術是由多載波調變演變而來，它具備了對抗符碼干擾的能力，且較能夠克服接收訊號時，所受到的通道衰減，並能在低接收器複雜度下提供高速傳輸，目前已有用在數位廣播，數位影像廣播等等。
在正交分頻多工系統中，快速複利葉轉換可使OFDM中的載波互相正交，故快速複利葉轉換為其重要的關鍵元件。
在本論文中，首先會介紹正交分頻多工的歷史和其基本的原理，接著介紹幾種FFT 的演算法和架構，再者是介紹其硬體設計和模擬，最後提出收發端的硬體架構和實現的方法。而在設計過程中，首先使用MATLAB程式來模擬功能是否正確及其效果，再來則是使用Verilog語言於Xilinx ISE環境下來模擬此電路。在模擬成功後，於Virtex-E之FGPA上合成實現本研究中所設計硬體電路。

Orthogonal Frequency Division Multiplexing （OFDM）comes from multi-carrier transmission technique. It not only alleviates the inter-symbol interference（ISI）, but also conquers the impact of the fading channel, and it can achieve high-data-rate transmission with low complexity. OFDM has already been implemented in Digital Audio Broadcasting (DAB) and the Terrestrial Digital Video Broadcasting（DVB-T）systems.
In an OFDM system, the carrier signals can be orthogonal by the Fast Fourier Transforms (FFT), so the FFT process is the key component in the OFDM system.
In this thesis, we firstly introduce the history and basic principles of OFDM, and describe several algorithms and implementation architectures of the FFT, and then discuss the hardware design and simulations. Furthermore, we depict the hardware architectures of transmitter and receiver and its implementations. In the process of designing transmitter and receiver, we first develop MATLAB programs to verify the correctness of their functions and the efficiency, and then derive Verilog HDL code in Xilinx ISE environment to describe these circuits. After functional and behavioral Verilog simulation is done, we synthesize and implement the hardware circuits designed in this thesis on Virtex-E FPGA.

Abstract in Chinese	I
Abstract in English	II
Acknowledgement	IV
Content	V
List of Figures	VIII
List of Tables	X

Chapter 1: Introduction	1
	1.1 Introduction and Motivation	1
	1.2 Structure of the Thesis	2 

Chapter 2: OFDM Basics	4
	2.1 Basic Principle of OFDM	4
               2.1.1 The Parallel Data Transmission	4
               2.1.2 Preview of OFDM	6
               2.1.3 The Concept of OFDM	9
           2.2 Mathematical Description of OFDM 	11
           2.3 OFDM System Analysis	14
               2.3.1 Transmitter	15
               2.3.2 Receiver	15
               2.3.3 Guard Interval	16
           2.4 Summary	19

Chapter 3: Review of FFT and QAM Algorithms	20
	3.1 Introduction	20
               3.1.1 The Concepts of FFT Algorithms	21
           3.2 The Fixed-Radix FFT Algorithms	22
               3.2.1 The Radix-2 FFT Algorithms	22
               3.2.2 The Radix-4 FFT Algorithms	29
           3.3 The Quadrature Amplitude Modulation (QAM)	34
           3.4 Summary	35

Chapter 4: The Architectures of FFT Process	36
	4.1 The Architecture of Butterfly Module	36
           4.2 Pipeline Architectures	37
               4.2.1 Introduction	37
               4.2.2 The Architecture of Multiple Path Delay Commutator	39
               4.2.3 The Architecture of Single Path Delay Feedback	41
           4.3 The Architecture of Memory-Based Architectures	42
               4.3.1 Introduction	42
           4.4 Summary	44

Chapter 5: Hardware Design and Simulation of an OFDM 
System	46
	5.1 OFDM Simulation in Matlab	46
           5.2 FFT Algorithm and Architecture Selection	51
           5.3 Simulation of FFT with Memory-Based Algorithm	52
           5.4 Summary	54

Chapter 6: Implementations of the Transmitter and Receiver 
of an OFDM System	55
	6.1 The Architecture of Transmitter	55
                6.1.1 The QAM Architecture	56
                6.1.2 The Architecture of FFT	58
                    6.1.2.1 Complete Architecture	58
                    6.1.2.2 The Architecture of Controller	59
                    6.1.2.3 The Architecture of RAM Bus	59
                    6.1.2.4 The Architecture of Butterfly Processor	61
                    6.1.2.5 The Architecture of Address Generator	62
                   6.1.2.6 The Architecture of Coefficient ROM	65
           6.2 The Architecture of Receiver	65
               6.2.1 The Architecture of dQAM	66
               6.2.2 The Architecture of IFFT	67
           6.3 The Results of Hardware Implementation	68
               6.3.1 The Simulation Results	69
               6.3.2 Hardware Implementation Results	70
           6.4 Summary	72

Chapter 7: Conclusions and Future Works	73
	7.1 Conclusions	73
	7.2 Future Works	74

References	75
                                    

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校內：2006-07-10公開
校外：2008-07-10公開

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