本論文中，我們針對不同應力形變之金氧半場效電晶體低頻雜訊(1/f 雜訊)進行研究及探討，從而了解不同應變矽工程下低頻雜訊之響應。透過低頻雜訊分析，除可觀測不同應變技術對於元件介面特性影響外，並能進一步闡述應變矽元件低頻雜訊的物理機制。論文區分三大主題進行探討:(i)雙軸伸張應變矽n型金氧半場效電晶體、(ii)雙軸壓縮應變矽鍺p型金氧半場效電晶體以及(iii)單軸伸張應變記憶技術之n型金氧半場效電晶體。
對於雙軸伸張應變矽n型金氧半場效電晶體來說，我們發現到對於應變矽厚度為20 nm時，其電子遷移率能夠提升約90%；另外一方面，我們發現應變矽層厚度在元件電性以及低頻雜訊皆扮演舉足輕重之角色，進而歸納出聯合機制可解釋雙軸伸張應力下所呈現之低頻雜訊理論。我們觀察到元件操作在弱反轉時，皆由載子擾動理論所主宰，而載子遷移率機制可用於描述元件操作於強反轉下之擾動行為。而於雙軸壓縮應變矽鍺p型金氧半場效電晶體的實驗中則發現，隨著鍺濃度的提升，除了元件效能進一步獲得提升外，其低頻雜訊則隨著鍺含量之便高而有所抑制，主要原因在其載子路徑被侷限於應變矽鍺層，進而減少載子在矽/二氧化矽介面之散射。最後，我們針對具有單軸伸張應變記憶技術之n型金氧半場效電晶體進行研究分析；實驗結果顯示採用應變記憶技術，可有效將單軸伸張應力傳遞至元件通道，進而使得n型金氧半場效電晶體之驅動電流能夠被有效提升，並且透過低頻雜訊分析技術，發現雖然比傳統元件多增加一道製程程序，但並未對介面特性產生嚴重退化。另一方面，我們也觀察到使用單軸伸張應變記憶技術之n型金氧半場效電晶體在標準化頻譜圖中能降低約四倍的雜訊頻譜，進而發現伸張應變能夠有效降低穿隧衰退長度以及庫倫散射，因此能有效改善其低頻雜訊品質。

In this dissertation, we investigate the low frequency noise (1/f noise) characterization of Si/SiO2 interface properties in strained-Si CMOS transistors. By utilizing the 1/f noise analysis, we can understand the response of interface properties in different strain technique transistors. The experiment of this dissertation is divided in three parts. First, we investigate and compare the effects of strained-Si layer thicknesses on interface characteristics in strained-Si nMOSFET fabricated on SiGe virtual substrate. It was observed that the 20 nm strained-Si cap layer thicknesses have about 90% enhancement compared with bulk nMOSFET. Besides, it can be found that strained-Si cap layer thickness plays an important role to affect the interface quality. Experiment results also show that the unified model, i.e. carrier number fluctuation model, including correlated mobility fluctuation is more suitable to interpret the mechanism of 1/f noise in strained-Si devices. Second, we observe the other one biaxial compressive strain-Si1-xGex pMOSFETs with the Ge content of 15% and 30%. Experiment results show the strained-SiGe pMOSFETs exhibited higher performance as Ge content increased. The strain-SiGe pMOSFETs with high Ge content exhibit lower 1/f noise performance due to carriers are confined in the SiGe buried channel and therefore can be removed interface scattering from Si/SiO2 interface. Finally, the use of 1/f noise to evaluate stress-memorization technique (SMT) induced-stress in nMOSFETs is investigated. As compared to device without SMT process, the comparable 1/f noise level obtained from strained Si nMOSFET with the SMT process indicates that adding the SMT process will not affect the Si/SiO2 interface quality. Moreover, it can be observed the normalized input-referred voltage noise spectral density (LSVG) of 40-nm SMT nMOSFETs in region I can reduce four times LSVG value compared with 1 um SMT nMOSFEs. It presents an intrinsic benefit of 1/f noise behavior stemming from SMT-induced more strain in short channel due to it can reduce tunneling attenuation length and Coulomb scattering coefficient.

[1.1] S. M. Sze, Physics of Semiconductor Devices. New Jersey: John Wiley & Sons, p.91, 1981.
[1.2] International Technology Roadmap for Semiconductors (ITRS), 2010 update, http://public.itrs.net/
[1.3] B. Yu, H. Wang, C. Riccobene, Q. Xiang; M. R. Lin,” Limits of gate-oxide scaling in nano-transistors,” in VLSI Symp. Tech. Dig., 2000, pp. 90-91.
[1.4] L.-A. Ragnarsson, L. Pantisano, V. Kaushik, S.-I. Saito, Y. Shimamoto, S. D. Gendt, M. Heyns, “The impact of sub monolayers of HfO/sub/ on the device performance of high-k based transistors,” IEDM Tech. Dig. pp. 4.2.1 - 4.2.4, 2003.
[1.5] D. A. Dallmann, K. Shenai, “Scaling constraints imposed by self-heating in submicron SOI MOSFET's,” IEEE Trans. Electron Dev. Vol. 42, 3, pp. 489 - 496, 1995.
[1.6] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, 1996.
[1.7] M. J. Deen and O. Marinov, “Noise in advanced electronic devices and circuits,” in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 3-12.
[1.8] L. K. J. Vandamme, “Noise as a diagnostic tool for quality and reliability of electronic devices,” IEEE Trans. Electron Devices, vol. 41, pp. 2176-2187, 1994.
[1.9] C. Claeys and E. Simoen, “Impact of advanced processing modules on the lowfrequency noise performance of deep-submicron CMOS technologies,” Microelectron. Reliab., vol. 40, pp. 1815-1821, 2000.
[1.10] A. D. van Rheenen, G. Bosman, and R. J. J. Zijlstra, “Low frequency noise measurements as a tool to analyze deep-level impurities in semiconductor devices,” Solid-State Electron., vol. 30, pp. 259-265, 1987.
[1.11] R. Jayaraman and C. G. Sodini, “A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon,” IEEE Trans. Electron Devices, vol. 36, pp. 1773-1782, 1989.
[1.12] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: a new perspective on individual defects, interface states and low-frequency (1/f) noise,” Advances in Physics, vol. 38, pp. 367-468, 1989.
[1.13] L. K. J. Vandamme, X. Li, and D. Rigaud, “1/f noise in MOS devices, mobility or number fluctuations?,” IEEE Trans. Electron Devices, vol. 41, pp. 1936-1945, 1994.
[2.1] J. L. Liou, and F. Schwierz, “RF MOSFET: recent advances, current status and future trends,” Solid-State Electron., vol. 47, pp. 1881-1895, 2003.
[2.2] A. A. Abidi, “RF CMOS comes of age,” in Proc. Symp. VLSI Circuits, 2003, pp. 113-116.
[2.3] Y. Taur T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, 1998.
[2.4] R. F. Pierret, Field effect devices, Addison-Wesley, Reading, 1990.
[2.5] D. K. Ferry and K. Bird, Electronic materials and device, Academic Press, 2001.
[2.6] Y. Tsividis, Operation and modeling of the MOS transistor, Second Edition, Oxford University Press, New York, 2003.
[2.7] F. Schwierz, Hei Wong and J. J. Liou, Nanometer CMOS, Pan Stanford Publishing, Singapore, 2010.
[2.8] M. B. Barron, “Low Level Currents in Insulated Gate Field Effect Transistors,” Solid-state Electron., vol.15, pp.293, 1972.
[2.9] W. M. Gosney, “Subthreshold Drain Leakage Current in MOS Field-Effect Transistors,” IEEE Trans. Electron Dev., vol. ED-19, pp.213, 1972.
[2.10] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 1998.
[2.11] M. Lundstrom, Fundamentals of carrier transport, 2nd ed, Cambridge University Press, 2000.
[2.12] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET’s: part I-effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, 1994.
[2.13] S. A. Schwarz and S. E. Russek, “Semi-empirical equations for electron velocity in silicon: part II-MOS inversion layer,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1634-1639, 1983.
[2.14] V. M. Agostinelli, Jr., H. Shin, and A. F. Tasch, Jr., “A comprehensive model for inversion layer hole mobility for simulation of submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 151-159, 1991.
[2.15]C. Kittel, Introduction to Solid State Physics, 4th ed., Wiley, New York, 1975, 261.
[2.16] F. Gámiz, J. B. Roldán J. E. Carceller, and P. Cartujo, “Monte Carlo simulation of remote-Coulomb-scattering-limited mobility in metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 82, pp. 3251-3253, 2003.
[2.17] G. Mazzoni, A. L. Lacaita, L. M. Perron, and A. Pirovano, “On surface roughnesslimited mobility in highly doped n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp. 1423-1428, 1999.
[2.18] D. K. Schroder, Semiconductor material and device characterization, 2nd ed., John Wiley & Sons, Inc., 1998.
[2.19] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the Universality of Inversion Layer Mobility in Si MOSFET's: Part I-Effects of Substrate Impurity Concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, 1994.
[2.20] S. M. Sze, Semiconductor devices, physics and technology, John Wiley and Sons, 1985.
[2.21] G. Ghibaudo, “New method for the extraction of MOSFET parameters,” Electronics Letters, vol. 24, pp. 543-545, 1988.
[2.22] S.C. Sun and J.D. Plummer, “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Trans. Electron Dev., vol. ED-27, pp.1497–1508, 1980.
[2.23] R.V. Booth, M.H. White, H.S. Wong and T.J. Krutsick, “The Effect of Channel Implants on MOS Transistor Characterization,” IEEE Trans. Electron Dev., vol. ED-34, pp.2501–2509, 1987.
[2.24] G. Ghibaudo, “New method for the extraction of MOSFET parameters,” Electronics Letters, vol. 24, pp. 543-545, 1988.
[2.25] H.G. Lee, S.Y. Oh and G. Fuller, “A Simple and Accurate Method to Measure the Threshold Voltage of an Enhancement-Mode MOSFET,” IEEE Trans. Electron Dev. ED-29, 346–348, Feb. 1982.
[2.26]G. Yaron and D. Frohman-Bentchkowsky, ‘Capacitance voltage characterization of poly Si-Si02-Si structures’, Solid-state Electron., vol.23, pp. 433-439, 1980.
[2.27]Narain Arora, MOSFET Modeling for VLSI Simulation: Theory and Practice, World Scientific Publishing, Singapore, 2007.
[2.28] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, ‘Charge accumulation and mobility in thin dielectric MOS transistors’, Solid-state Electron., vol.25, pp. 833-841,1982.
[2.29] J. Kooman, ‘Investigation of MOST channel conductance in week inversion’, Solid-State Electron., vol.16, pp. 801-810, 1973.
[2.30] M. S. Liang, J. Y. Choi, P. K. KO, and C. M. Hu, ‘Inversion-layer capacitance and mobility of very thin gate-oxide MOSFETs’, IEEE Trans. Electron Devices, vol. ED-33, pp. 409-413, 1986.
[2.31] P.-M. D. Chow and K.-L. Wang, ‘A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFETs’, IEEE Trans. Electron Devices, vol. ED-33, pp. 1299-1304, 1986.
[2.32] G. Sh. Gildenblat, C.-L. Huang, and N. D. Arora, ‘Split C-V measurements of low temperature MOSFET inversion layer mobility,’ Cryogenics, 29, pp. 1163-1166, 1989.
[2.33] C. L. Huang, J. Faricelli, and N. D. Arora, ‘A new technique for measuring MOSFET inversion layer mobility’, IEEE Trans. Electron Devices, vol.ED-40, pp. 11 34-1 139, 1993.
[2.34] A. Hairapetian, D. Gitlin, and C. R. Viswanathan, ‘Low-temperature mobility measurements on CMOS devices’, IEEE Trans. Electron Devices, vol.ED-36, pp. 1448-1445 (1989)
[2.35] R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, 1974
[2.36] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, “Ion implanted MOSFETs with very short channel lengths,” in IEDM Tech. Dig., 1973, pp. 152-155.
[2.37] D. L. Critchlow, “MOSFET scaling – the driver of VLSI technology,” Proc. of the IEEE, vol. 87, pp.659-667, 1999.
[2.38] S. Takagi, M. Iwase, and A. Toriumi, “On the universality of inversion-layer mobility in n- and p-channel MOSFETs ,” in IEDM Tech. Dig., 1988, pp. 398-401.
[2.39] D. K. Nayak and S. K. Chun, “Low-field hole mobility of strained Si on (100) Si1–xGex substrate,” Appl. Phys. Lett. 64, pp. 2514-2516, 1994.
[2.40] T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si layers on Si1−x Gex substrate, “ Appl. Phys. Lett. 63, pp. 186-188, 1993.
[2.41] K. Rim, J. Chu, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott. K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan. D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs,” in VLSI Symp. Tech. Dig., 2002, pp. 98-99.
[2.42] D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang, and K. P. MacWilliams, “High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si,” Appl. Phys. Lett. 62, 2853, 1993
[2.43] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, pp. 1567–1577, Aug. 1996.
[2.44] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 101, pp. 104503, 2007.
[2.45] N. Mohta, and S. E. Thompson, “Mobility Enhancement,” IEEE Circuits and Devices Magazine, vol. 21, pp. 18–23, 2005.
[2.46] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., 2005, pp. 129–132.
[2.47] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uniaxial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si,” in IEDM Tech. Dig., 2004, pp. 225–228.
[2.48] S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for performance enhancement of Si MOSFETs,” in IEDM Tech. Dig., 1997, pp. 219–222.
[2.49] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., 2004, pp. 221–224.
[2.50] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A Logic Nanotechnology Featuring Strained-Silicon,” IEEE Electron Device Lett., vol. 25, pp. 191–193, 2004.
[2.51] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride Films,” in Tech. Dig. IEDM, 2004, pp. 213-216.
[2.52] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors,” in IEEE Tran. Electron Devices, vol. 54, no. 4, April 2007.
[2.53] K.-W. Ang, K.-J. Chui, V. Bliznetsov, Y. Wang, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M.-F. Li, G. Samudra, and Yee-Chia Yeo, “Thin Body Silicon-on-Insulator N-MOSFET with Silicon-Carbon Source/Drain Regions for Performance Enhancement,” in Tech. Dig. IEDM, 2005, pp. 497 - 500.
[2.54]Y. Jeon, G.C. F. Yeap, P. Grudowski, T. Van Gompel, J. Schmidt, M. Hall, B. Melnick, M. Mendicino, S. Venkatesan, “The impact of STI mechanical stress on the device performance of 90 nm technology node with different substrates and isolation processes,” in VLSI Symp. Tech. Dig., 2003, pp. 164-165.
[2.55] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, M. Haond, “A low cost drive current enhancement technique using shallow trench isolation induced stress for 45-nm node,” in VLSI Symp. Tech. Dig., 2006, pp. 82 - 83.
[2.56] P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, “Fundamentals of Silicon Material Properties for Successful Exploitation of Strain Engineering in Modern CMOS Manufacturing,” IEEE Trans. Elect. Device., vol. 53, pp. 944-964, 2006.
[2.57] A. Steegen, K. Maex, “Silicide-induced stress in Si: origin and consequences for MOS technologies,” in Mater. Sci. and Eng. R, pp. 1-53, 2002.
[2.58] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf and F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS,” in VLSI Symp. Tech. Dig., 2006, pp. 78 - 79.
[2.59] C. Ortolland, Y. Okuno, P. Verheyen, C. Kerner, C. Stapelmann, M. Aoulaiche, N. Horiguchi, and T. Hoffmann, “Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process,” IEEE Trans. Elect. Device., vol. 56, pp. 1690-1697, 2009.
[3.1] M. von Haartman, M. Östling, Low-Frequency Noise in Advanced MOS Devices, Springer, 2007.
[3.2] R. Landauer, “The noise is the signal,” Nature, vol. 392, pp. 658-659, 1998.
[3.3] F. N. Hooge, “1/f Noise Sources,” IEEE Trans. Electron Devices, vol. 41, pp.1926-1935, 1994.
[3.4] T. Musha, S. Sata and M. Yamamoto, Noise in Physical Systems and 1/f Fluctuation, IOS Press, Japan, 1992.
[3.5] A. van der Ziel. Noise in Solid State Devices and Circuits. John Wiley & Sons, New York, 1986.
[3.6] N. Giordano, “Defect motion and low-frequency noise in disordered metals,” Solid State Sci., vol. 3, no. 1, p. 27, 1989.
[3.7] J. B. Johnson, “Thermal agitation of electricity in conductors,” Phys. Rev., vol. 32, pp. 97-109, 1928.
[3.8] H. Nyquist, “Thermal agitation of electric charge in conductors,” Phys. Rev., vol. 32, pp. 110-113, 1928.
[3.9] A. van der Ziel, J. B. Anderson, A. N. Birbas, W. C. Chen, P. Fang, V. M. Hietala, C. S. Parka, P. R. Pukite, M. F. T., X. Wua, J. Xu and A. C. Young, “Shot noise in solid state diodes,” Solid-State Electron, 29, p. 1069, 1986.
[3.10] K.K Hung, P.K. Ko, C.M. Hu,”A unified model for the flicker noise in metal-oxide -semiconductor field-effect transistors”, IEEE Trans. Electron Devices, p654, 1990.
[3.11] P. Dutta and P. M. Horn, Low-frequency fluctuations in solids: 1/f noise, Rev. Mod. Phys. 53, 497-516 (1981).
[3.12] F. N. Hooge, “1/f noise is no surface effect,” Phys. Lett. A, vol. 29a, pp. 139-140, 1969.
[3.13] F. N. Hooge, Discussion of recent experiments on 1/f noise, Physica vol.60, pp.130-144, 1972.
[3.14] F. N. Hooge, T. G. M. Kleinpenning, and L. K. J. Vandamme, “Experimental studies on 1/f noise,” Rep. Prog. Phys., vol. 44, pp. 479-531, 1981.
[3.15] S. Machlup, “Noise in semiconductors: spectrum of a two-parameter random signal,” J. Appl. Phys., vol. 25, pp. 341-343, 1954.
[3.16] Y. A. Allogo, M. Marin, M. de Murcia, P. Llinares, D. Cottin, “1/f noise in 0.18 m technology n-MOSFETs from subthreshold to saturation,” Solid-State Electronics, vol. 46, pp. 977–983, 2002.
[3.17] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, J. Brini, “Improved Analysis of Low Frequency Noise in Field-Effect MOS Transistors,” Phys. Stat. Sol. (A), vol. 124, pp. 571-581, 1991.
[4.1] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, and M. Koga, “Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-On-Insulator (Strained-SOI) MOSFET,” in IEDM Tech. Dig., 2003, pp. 57-60.
[4.2] S. L. Wu, Y. P. Wang, and S. J. Chang, “Controlled misfit dislocation technology in strained silicon MOSFETs,” Semicond. Sci. Technol., vol. 21, pp. 44-47, 2006.
[4.3] W.-C. Hua, M. H. Lee, P. S. Chen, S. Maikap, and C. W. Liu, “Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 25, pp. 693–695, 2004.
[4.4] W.-C. Hua, M. H. Lee, P. S. Chen, S. Maikap, and C. W. Liu, “Threading dislocation induced low frequency noise in strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 25, pp. 667–669, 2005.
[4.5] K. Fobelets,S. L. Rumyantsev, M. S. Shur, and S. H. Olsen, “Influence of the Ge concentration in the virtual substrate on the low frequency noise in strained-Si surface n-channel metal–oxide–semiconductor field-effect transistors” J. Appl. Phys., vol. 103, pp. 044501, 2008.
[4.6] E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C. Claeys, “On the beneficial impact of tensilestrained silicon substrates on the low-frequency noise of n-channel metal–oxide–semiconductor transistors,” Appl. Phys. Lett., vol. 86, pp. 223509, 2005.
[4.7] M. P. Lu, W. C. Lee, M. J. Chen “Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal–oxide–semiconductor transistors,” Appl. Phys. Lett., vol. 88, pp. 063511, 2006.
[4.8] W. A. Hill, and C. C. Coleman, “A single frequency approximation for interface-state density determination, ” Solid-State Electron., vol. 23, pp. 987-993, 1980.
[4.9] A. L. McWhorter, Semiconductor Surface Physics, R. H. Kinston, Ed. Philadelphia, PA: Univ. Pennsylvania Press, 1957.
[4.10] A. Stesmans, “Structural relaxation of Pb defects at the (111) Si/SiO2 interface as a function of oxidation temperature: the Pb -generation–stress relationship,” Phys. Rev. B, vol. 48, pp.2418-2435, 1993.
[4.11] A. Stesmans and V. V. Afanas'ev, “Thermally induced interface degradation in (111) Si/SiO2 traced by electron spin resonance,” Phys. Rev. B, vol. 54, pp, R11129–R11132, 1996.
[4.12] A. Stesmans, D. Pierreux, R. J. Jaccodine, M.-T. Lin, and T. J. Delph, “Influence of in situ applied stress during thermal oxidation of (111) Si on Pb interface defects,” Appl Phys Lett vol. 82, pp. 3038-3040, 2003.
[4.13] A. Stesmans, P. Somers, V. V. Afanas’ev, C. Claeys, and E. Simoen, “Inherent density of point defects in thermal tensile strained (100) Si/SiO2 entities probed by electron spin resonance” Appl. Phys. Lett., vol. 89, pp. 152103, 2006.
[4.14] E. Simoena and C. Claeys, “On the ficker noise in submicron silicon MOSFETs,” Solid-State Electron., vol. 43, pp. 865-882, 1992.
[4.15] Y. M. Lin, S. L, Wu, S. J. Chang, P. S. Chen and C. W. Liu, “Hole Confinement and 1/ f Noise Characteristics of SiGe Double-Quantum-Well p-Type Metal–Oxide–Semiconductor Field-Effect Transistors,” Jpn. J. Appl. Phys., vol. 45, pp. 4006-4008, 2006.
[4.16] C. H. Lee, S. L. Wu and S. J. Chang, “Improved performance of SiGe doped-channel field-effect transistor using inductively coupled plasma etch,” Semicond. Sci. Technol., vol. 19, pp. 1053–1056, 2004.
[4.17] S. Verdonckt-Vandebroek, E. F. Crabbe´, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, and J. B. Johnson,” SiGe-Channel Heterojunction p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp.90-101, 1994.
[4.18] M. J. Prest, M. J. Palmer, G. Braithwaite, T. J. Grasby, P. J. Phillips, O. A. Mironov, E. H. C. Parker, and T. E. Whall, “Si/Si0.64Ge0.36/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise,” in Proc. ESSDERC, 2001, pp. 179-182.
[4.19] T. Tsuchiya, T. Matsuura1 and J. Murota, “Low-Frequency Noise in Si1-xGex p-Channel Metal Oxide Semiconductor Field-Effect Transistors,” Jpn. J. Appl. Phys., vol. 40, pp. 5290-5293, 2001.
[4.20] M. von Haartman, A.-C. Lindgren, P.-E. Hellstro¨m, B. G. Malm, S.-L. Zhang, and M. Östling, “1/f noise in Si and Si0.7Ge0.3 pMOSFETs,” IEEE Trans. Electron Devices, vol. 50, pp.2513-2519, 2003.
[4.21] S. Ogura, C. F. Codella, N. Rovedo, J. F. Shepard, and J. Riseman, “A half micron MOSFET using double implanted LDD,” in IEDM Tech. Dig., 1982, pp. 718-722.
[4.22] P. W. Li, E. S. Yang, Y. F. Yandg, J. O. Chu, and B. S. Meyerson, “SiGe pMOSFET’s with gate oxide fabricated by microwave electron cyclotron resonance plasma processing,” IEEE Electron Device Lett., vol. 15, pp. 402-405, 1994.
[4.23] I. S. Goh, J. F. Zhang, S. Hall, W. Eccleston, and K. Werner, “Electrical properties of plasma-grown oxide on MBE-grown SiGe ,” Semicond. Sci. Technol., vol. 10, pp. 818-828, 1995
[4.24] P. W. Li, H. K. Liou, E. S. Yang, S. S. Lyer, T. P. Smith III, and Z. Lu, “Formation of stoichiometric SiGe oxide by electron cyclotron resonance plasma,” Appl. Phys. Lett., vol. 60, pp. 3265-3267, 1992.
[4.25] Deepak K. Nayak, Ph. D. Dissertation, University of California Los Angeles, 1992
[4.26] F. K. LeGoues, R. Rosenberg, T. Nguyen, J. Himpsel, and B. S. Meyerson, “Oxidation studied of SiGe,” J. Appl. Phys., vol. 65, p. 1724 - 1728, 1989.
[4.27] G. K. Dalapati, S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, Y. L. Tsang, R. Agaiby, A. G. O’Neill, P. Dobrosz, and S. J. Bull “Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp.1142-1152, 2006.
[4.28] K. Terada and H. Muta, “A New Method to Determine Effective MOSFET Channel Length,” Jpn. J. Appl. Phys., vol.18, pp. 953-959, 1979.
[4.29] J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, “A new method to determine MOSFET channel length,” IEEE Electron Device Lett., vol.1 pp.170-173, 1980.
[4.30] Y. A. Allogo, M. Marin, M. D. Murcia, P. Llinares, and D. Cottin, “1/f noise in 0.18 μm technology n-MOSFETs from subthreshold to saturation,” Solid-State Electron., vol. 46, pp. 977-983, 2002.
[4.31] J. J.-Y. Kuo, W. Chen, and P. Su, “Enhanced Carrier-Mobility-Fluctuation Origin Low-Frequency Noise in Uniaxial Strained PMOSFETs,” IEEE Electron Device Lett., vol. 31, pp. 497–499, 2011.
[4.32] S. T. Pantelides, L. Tsetseris, M. J. Beck, S. N. Rashkeev, G. Hadjisavvas, I. G. Batyrev, B. R. Tuttle, A. G. Marinopoulos, X. J. Zhou, D. M. Fleetwood, and R. D. Schrimpf, “Performance, reliability, radiation effects, and aging issues in microelectronics from atomicscale physics to engineering-level modeling,” in Proc. ESSDERC, 2009, pp. 48–55.
[4.33] K. K. Hung, P. K. Ko, and C. Hu, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. Electron Devices, vol. 37, pp.654-665, 1990.
[5.1] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron. Reliab., vol.42, pp. 573-582, 2002.
[5.2] Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors for analog applications,” IEEE Trans. Electron Devices vol. 48, pp,921 – 927, 2001.
[5.3] K.-W. Ang, K.-J. Chui, V. Bliznetsov, C.-H. Tung, A. Du, N. Balasubramanian, G. Samudra, M. F. Li, and Y.-C. Yeo, ”Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors,” Appl. Phys. Lett., vol. 86, pp. 093102, 2005.
[5.4] S. L. Wu, Y. M. Lin, S. J. Chang, S. C. Lu, P. S. Chen, and C. W. Liu, “Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology,” IEEE Electron Device Lett., vol. 27, pp. 46-48, 2006.
[5.5] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors,” IEEE Trans. Electron Devices, vol. 54, pp. 814–821, 2007.
[5.6] K. Fobelets, S. L. Rumyantsev, M. S. Shur, and S. H. Olsen, “Influence of the Ge concentration in the virtual substrate on the low frequency noise in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 103, pp. 044501, 2008.
[5.7] C.-H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M.-S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application,” in VLSI Symp. Tech. Dig., 2004, pp. 56–57.
[5.8] A. Wei, M. Wiatr, A. Gehring, R. Boschke, C. Scott, J. Hoentschel, S. Duenkel, M. Gerhardt, T. Feudel, M. Lenski, F.Wirbeleit, R. Otterbach, R. Callahan, G. Koerner, N. Krumm, D. Greenlaw, M. Raab, and M. Horstmann, “Multiple stress memorization in advanced SOI CMOS technologies,” in VLSI Symp. Tech. Dig., 2007, pp. 216–217.
[5.9] T. Ueno, H. S. Rhee, H. Lee, M. S. Kim, H. S. Cho, H. S. Baik, Y. H. Jung, H. W. Lee, H. S. Park, C. K. Lee, G.-J. Bae, and N.-I. Lee, “Improved 1/f Noise Characteristics in Locally Strained Si CMOS using Hydrogen-Controlled Stress Liners and Embedded SiGe,” in VLSI Symp. Tech. Dig., 2006, pp. 104-105.
[5.10] Y. P. Wang, S. L. Wu, and S. J. Chang, “Low-Frequency Noise Characteristics in Strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 28, pp.36-38, 2007.
[5.11] M. von Haartman, , D. Wu, B. G. Malm, P. -E. Hellström, S. -L. Zhang and M. Östling, “Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics,” Solid-State Electron., vol. 48, pp. 2271-2275, 2004.
[5.12] M. Goto, K. Tatsumura, S. Kawanaka, K. Nakajima, R. Ichihara, Y. Yoshimizu, H. Onoda, K. Nagatomo, T. Sasaki, T. Fukushima, A. Nomachi, S. Inumiya, H. Oguma, K. Miyashita, H. Harakawa, S. Inaba, T. Ishida, A. Azuma, T. Aoyama, M. Koyama, K. Eguchi, and Y. Toyoshima, “Impact of Tantalum Composition in TaC/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL,” in VLSI Symp. Tech. Dig., 2008, pp. 132-133.
[5.13] L. K. J. Vandamme, “Noise as a diagnostic tool for quality and reliability of electronic devices,” IEEE Trans. Electron Devices, vol. 41, pp. 2176-2187, 1994.
[5.14] L. K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know About 1/f Noise in MOSTs?,” IEEE Trans. Electron Devices, vol. 55, pp. 3070-3085, 2008.
[5.15] J. Zhuge, R. Wang, R. Huang, Y. Tian, L. Zhang, D.-W. Kim, D. Park, and Y. Wang, “Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs,” IEEE Electron Device Lett., vol. 30, pp.57-60, 2009.
[5.16] F. Crupi, B. Kaczer, R. Degraeve, V. Subramanian, P. Srinivasan, E. Simoen, A. Dixit, M. Jurczak, and G. Groeseneken, “Reliability Comparison of Triple-Gate Versus Planar SOI FETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2351-2357, 2006.
[5.17] H. Y. Lin, S. L. Wu, S. J. Chang, Y. P. Wang, and C. W. Kuo, “Low-frequency noise of strained-Si nMOSFETs fabricated on a chemical–mechanical-polished SiGe virtual substrate,” Semicond. Sci. Technol., vol. 23, pp.105022, 2008.
[5.18] J.-M. Peransin, P. Vignaud, D. Rigaud, and L.. J. Vandamme, “l/f Noise in MODFET’s at Low Drain Bias,” IEEE Trans. Electron Devices, vol. 37, pp. 2350-2253, 1990.
[5.19] J. J.-Y. Kuo, W. P.-N. Chen, and P. Su, “Impact of Uniaxial Strain on Low-Frequency Noise in Nanoscale PMOSFETs,” IEEE Electron Device Lett., vol. 30, pp. 672-674, 2009.
[5.20] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proc. of EDST, 2007, pp. 149–152.
[5.21] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, 2005.
[5.22] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, pp. 052108–1–3, Jan. 2006.