本研究利用化學氣相沉積法(Chemical Vapor Deposition, CVD)，以鋅粉與銦粉混合，通入氧氣當反應氣氛，並改變製程溫度於650oC與550oC下成長摻雜銦的氧化鋅結構。分別以掃描式電子顯微鏡(Scanning Electron Microscopy, SEM)和穿透式電子顯微鏡(Transmission Electron Microscopy, TEM)分析成長出摻雜銦的氧化鋅結構表面形貌與微結構分析，配合能量分散分析儀 (Energy Dispersive Spectrometer, EDS)與歐傑電子能譜儀 (Auger Electron Spectrometer, AES)，分析結構的元素組成來探討不同成長溫度下摻雜銦濃度的多寡，以及對於氧化鋅結構上的影響。利用電子束微影製作電性量測元件，來探討摻雜銦的氧化鋅結構導電性質，利用變溫量測電性方式探討電阻對溫度的變化來探究半導體中載子傳輸行為，最後利用Metal oxide semiconductor field effect transistor (MOSFET)結構，配合側向閘極電極結構來探討摻雜銦氧化鋅結構的載子濃度，並與未摻雜的氧化鋅奈米線作為比較，可證實化學氣相沉積法在較低溫的製程下銦可成功摻雜進入氧化鋅內，並可藉由溫度的調控改變銦的摻雜量使氧化鋅有不同的導電性質，並影響到氧化鋅結構的方向成長。

In this research, various Indium doped ZnO nanostructures were synthesized on Si substrate by chemical vapor deposition (CVD). The mixed powder of zinc and indium were used as source and O2 gas were used as a reaction gas. Growth temperature were set at 650oC and 550oC to grow indium doped ZnO structures. The morphology and microstructure of the products were analyzed by Scanning Electron Microscopy and Transmission Electron Microscopy, Energy Dispersive Spectrometer or Auger Electron Spectrometer were employed to analyze elemental distribution and the influence of growth temperature on indium concentration and ZnO structures is discussed. The electrical properties of ZnO nanostructure were measured where pattern were made by e-beam lithography. Temperature dependence of resistance of nanostructure at various temperatures was measured and discussed in relation to their nanowire Metal oxide semiconductor field effect transistor with side gate electrodes which developed by e-beam lithography to measure carrier concentrations of different ZnO structures by using field effects. By comparing with undoped ZnO nanowires, doped ZnO structures were confirmed to provide higher carrier concentration. Therefore CVD process is demonstrated to dope indium into ZnO successfully and increase carrier concentration. The growth direction of ZnO nanostructures can also be varied by growth temperature.

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