資料加密標準(Data Encryption Standard, DES)演算法，為一種對稱型金鑰加密演算法，由美國國家標準與技術研究院(NIST)於1976年訂定為資料處理標準，由於DES本身的金鑰長度過低容易被破解，日後因此衍生出三重資料加密演算法(3DES)，透過增加金鑰長度來避免被輕易的破解。近年來，無線通訊技術發展的越來越完善，在許多不同的應用層面應用中，不只資料傳輸速率越來越高，資料安全也有一定的重要性，要在高資料傳輸速率的情況下仍將每筆資料安全加密，是現今面臨的挑戰。因此，如何實現兼具低成本與高資料傳輸速率的3DES-CBC硬體電路，為本篇論文的研究目標。
一般針對網際網路安全協定(IPsec)網路封包加密的硬體電路，使用3DES-CBC的架構，大多數一次只能夠對單一網路通道(network channel)單一封包裡的資料進行加密。然而，在這些電路架構中，使用來提升電路加密速率的方法有限，整體電路的加密速率提升的程度也非常有限，若是直接用管線化架構來提升電路速率，反而會受到封包加密資料前後相依性(dependency)的影響，造成硬體資源的浪費。
在本篇論文中，為了提高整體電路加解密過程的速率，利用能夠同時加密多個網路通道的封包資料，或者是同時加密單一網路通道不同封包資料的方法，錯開加密資料的前後相依性，並且將演算法架構分層管線化，將3DES-CBC演算法內部的置換盒(S-Box)，依據其原理以及計算過後的延遲，在其中安插相對的暫存器，使得整體電路能達到更快的時脈頻率，資料產生速率也能因此增加。本篇論文實現於ASIC與 Xilinx 系列的FPGA上，並與文獻探討時脈頻率、面積、資料產生速率和面積使用效率這四項數據。

To implement a high performance circuit for encrypting network channel packet, this paper proposes a method to schedule the packet data and different pipelined 3DES-CBC architectures. Use the scheduling of different packet data of multiple network channels to remove the dependency of encrypted data. Control the sequence of channel packet to allocate the hardware resources of pipelined 3DES-CBC circuit to each channel. We also divide the critical path of S-Box into several paths which are balanced to make pipelined architecture have higher clock frequency and throughput. Using the proposed architecture, a throughput of 44.75 Gbps for 3DES-CBC pipelined circuit can be achieved in ASIC TSMC 130nm process. According to the FPGA implementation result, the throughput of design can reach 20.11 Gbps on Virtex-4 XC4VLX25.

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