自1960 年代金氧半場效電晶體（MOSFET）成為積體電路主流元件以來，半導體產業長期仰賴尺寸微縮以提升效能與整合密度。然而，當元件進入奈米尺度後，傳統微縮逐漸遇到瓶頸，只透過平面或是單一方向的結構優化已經很難讓CMOS 的效能成長。為了突破上述限制，3D堆疊NMOS-on-PMOS 結構（也稱為互補式堆疊電晶體，CFET）在固定平面面積下提升邏輯密度，成為後續節點的重要候選架構。此外，選用鍺(Ge)材料，是因為它具有高載子遷移率，因而被視為適合當作CFET的高效通道材料。但是鍺(Ge)通道具備高載子遷移率潛力，理論上可在低電壓下提供更高驅動電流；然而，其氧化層不穩定與介面缺陷控制困難，使得high-k/Ge處理與低熱預算整合成為關鍵課題。
在本研究，我們利用低溫晶圓鍵結的技術，將兩片GeOI與GeSOI晶圓鍵合，實現Ge/GeCFET 的垂直堆疊整合，本研究採用晶圓鍵結技術建立上下層通道之3D結構。本研究採用(100)Ge與(111)Ge基板進行鍵結，旨在利用晶向作為可控變因，系統性比較晶向對鍺通道載子遷移率（電子/電洞）及其對元件驅動能力之影響，同時評估high-k/Ge 介面品質（如C–V frequency dispersion、hysteresis、以及由 G–V 萃取之 Dit）在不同晶向下的差異。透過GeOI元件與MOSCAP對照分析，建立適用於Ge/Ge CFET之晶向選擇依據與製程最佳化方向。本論文首先以介面工程改善閘極介電質與通道材料之界面品質，降低介面缺陷相關效應；其次調整離子佈植條件（如劑量、能量等）以控制摻雜分佈，進而優化後續活化流程，提升元件之臨界電壓控制與整體電性穩定度。
最後，本研究進一步針對所製備之Ge基元件於低溫條件下之電性行為進行系統性探討。探討低溫特性之必要性在於：其一，先進節點與三維堆疊元件（如 CFET）之實際運作可能面臨更嚴苛的熱管理與局部溫度梯度，元件於低溫或溫度變動下的穩定性與可預期性因此成為關鍵；其二，溫度降低會顯著改變載子散射、載子統計分佈與缺陷態之捕放電動力學，使得臨界電壓漂移、次臨界擺幅、漏電與遲滯等現象可能呈現與室溫不同之趨勢，進而影響模型建立與可靠度評估；其三，低溫量測可用以區分傳輸主導機制（如熱激發、穿隧與陷阱輔助傳輸）並揭示介面缺陷（Dit）與陷阱效應對元件電性之貢獻。基於上述考量，本研究透過低溫Id–Vg/Id–Vd量測與參數萃取，評估層轉移所製備Ge基元件於低溫下之開關行為與電性穩定度，據以驗證其在低溫操作與先進元件整合情境中的可行性。

Since the 1960s, metal–oxide–semiconductor field-effect transistors (MOSFETs) have served as the dominant device platform for integrated circuits, and the semiconductor industry has relied on geometric scaling to improve performance and integration density. However, as device dimensions have entered the nanometer regime, conventional scaling has encountered fundamental limitations, and performance gains can no longer be sustained by planar designs or one-directional structural optimizations alone. To overcome these constraints, three-dimensional stacked NMOS-on-PMOS architectures, also referred to as complementary FETs (CFETs), have emerged as a leading candidate for future technology nodes because they can increase logic density without expanding the lateral footprint. In addition, germanium (Ge) is an attractive channel material due to its high carrier mobility, which in principle enables higher drive current at reduced operating voltage. Nevertheless, the instability of Ge native oxides and the difficulty of controlling interface defects make high-k/Ge interface processing and low-thermal-budget integration critical challenges.

In this work, we realize vertical Ge/Ge CFET integration by low-temperature wafer bonding, in which two wafers—GeOI and GeSOI—are bonded to form a three-dimensional stacked channel structure. To use crystal orientation as a controlled variable, Ge(100) and Ge(111) substrates are bonded and systematically compared to elucidate orientation-dependent carrier transport (electron/hole mobility) and its impact on device drive capability. Meanwhile, the high-k/Ge interface quality is evaluated across different orientations by capacitance–voltage (C–V) frequency dispersion, hysteresis, and interface trap density (Dit) extracted from conductance–voltage (G–V) measurements. Through a combined analysis of GeOI devices and MOS capacitors (MOSCAPs), this study establishes guidelines for crystal-orientation selection and process optimization for Ge/Ge CFET integration. Furthermore, interface engineering is first employed to improve the dielectric/channel interface and mitigate interface-defect-related effects; subsequently, ion implantation conditions (e.g., dose and energy) are optimized to tailor the dopant profile, thereby improving the subsequent activation process and enhancing threshold-voltage control and overall electrical stability.

Finally, we conduct a comprehensive investigation of the low-temperature electrical behavior of the fabricated Ge-based devices. Low-temperature characterization is essential for several reasons: (i) advanced nodes and three-dimensional stacked devices (e.g., CFETs) may experience more stringent thermal management constraints and local temperature gradients, making device predictability and stability under reduced or varying temperature increasingly critical; (ii) decreasing temperature significantly alters carrier scattering, carrier statistics, and trap capture/emission kinetics, leading to trends in threshold-voltage shift, subthreshold swing, leakage current, and hysteresis that can differ from room-temperature behavior and thus affect compact modeling and reliability assessment; and (iii) low-temperature measurements help distinguish dominant transport mechanisms (e.g., thermally activated transport, tunneling, and trap-assisted conduction) and clarify the contributions of interface traps (Dit) and trapping effects to device characteristics. Based on these considerations, low-temperature Id–Vg/Id–Vd measurements and parameter extraction are performed to evaluate the switching behavior and electrical stability of layer-transfer-fabricated Ge devices at cryogenic temperatures, thereby validating their feasibility for low-temperature operation and advanced device-integration scenarios.

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