近年來對於無線通訊系統之研究有著卓越的發展，而目前對於射頻前端系統，低功率、低成本與小體積為現今無線通訊的主要訴求，為了實現以上的條件，便需要先進之製程技術與創新的電路設計來互相配合。在射頻收發器模組中，3dB耦合電路、次諧波混頻器與壓控振盪器對於頻率轉換的特性扮演著重要角色，但這些關鍵零組件，在傳統架構中不論是電路大小或是效能方面都有值得研究改善的空間；其中，3dB 耦合器經常使用於平衡式次諧波混頻器或放大器的架構中，來達到功率平衡輸出或結合的目的，但是其所需面積經常過大而不易實現於晶片中；另一方面，這些非線性元件經常產生諧波干擾訊號，故輸出端耦合器又肩負著諧波抑制的功能 因此，本論文針對微型化耦合器來做一研究並將其應用於單晶次諧波混頻器上，最後更進一步將諧波抑制功能予以整合。另一方面，採用CMOS 製程技術實現壓控震盪器在操作電壓、消耗功率及系統成本等考量皆具有一定之優勢；但由於矽基板的高頻介電損耗相較於其他基板製程來的高，且隨著製程的進步，元件雜訊也相對提高，這些因素都造成相位雜訊的退化。故論文中，也將探討CMOS 壓控振盪器架構之設計與實現，並持續針對其操作電壓、相位雜訊、功率消耗等特性做一改良。在3dB 耦合電路研究、實現與應用方面，論文中提出一個使用電感、電容集成元件的新穎式九十度耦合器。相較於傳統小型化耦合器，除了更有效節省面積外，也提供了一個更為寬頻的操作頻寬(~18%)。另外，此對稱性架構不需要任何穿孔到地，這在印刷電路板或是其他高頻基板實現時，將帶來更多便利性且較不耗費面積；而藉由ABCD 矩陣分析，我們可證明此架構為一個理想九十度耦合器。
此外，我們也進一步地研製具有諧波抑制功能的90 度和180 度小型化耦合器，所提出兩個2.45GHz 耦合器，利用諧波頻率拒斥共振器來同時達到小型化耦合器所需高、低通特性和所需頻帶諧波抑制的功能，進而減少集成元件的使用。除此之外，我們將提出的微型化耦合器成功實現於一個單晶Ka 頻帶的平衡式次諧波混頻器上，在此提出的架構中，利用LO 3 次諧波進行混頻，其相較於傳統平衡式混頻器利用2 次諧波混頻的方式，可進一步將LO 操作頻率由Ku band 減少至X band，這將有利於減輕系統上本地震盪源之負擔;同時，也希望將傳統高頻系統中三倍頻器的功能來加以取代，以實現系統高度整合的目的。在本地振盪源研究方面，我們設計應用於S頻段與C頻段三個CMOS震盪器，並藉由其量測數據來探討在不同架構和應用上其特性表現。論文中，提出一個低操作電壓1V，採用九十奈米製程的共源極PMOS單端壓控振盪器，並加上靜電防護於此電路中；此架構利用汲極電感回授與寄生電容產生負電阻並採用單顆PMOS做為振盪源的主體，將元件雜訊予以最小化；當操作頻率在1.75-GHz頻段，整體功率消耗5.54mW時，有-107dBc/Hz@1MHz的相位雜訊。另外，我们提出使用交錯耦合式PMOS尾電流源的技術，將傳統考畢茲架構中電流源退化相位雜訊的缺點來做一改善，並將其成功實現於一個5-GHz相位雜訊-100.3dBc@100kHz的考畢茲差動壓控振盪器。最後，吾人則是利用閘極電感回授技術來增強負電阻效應，改善傳統考畢茲振盪器起振條件，進而降低原先的消耗功率，並成功實現於一個7.9-GHz、功率消耗4.9mW的全PMOS考畢茲差動壓控振盪器。

Wireless communications research has experienced a remarkable renaissance in the last decade. Low power, low cost, and a compact size are the essential requirements for modern RF frond-end systems. In RF transceiver, voltage controlled oscillators (VCOs) and 3dB couplers are essential blocks but these components based on conventional architectures still have several issues and are worth to be investigated. The physically size of the 3dB couplers are too larger to be integrated on a chip. In
addition, the couplers connected to the output terminal of the balanced SHM or power amplifier must provide a significant harmonic rejection. Moreover, VCO using CMOS technology has the advantages on the cost, low supply voltage and low power consumption but silicon lossy substrate and worse device noise would degrade significantly the phase noise. Therefore, how to improve further the performance of CMOS VCOs is also worth to be studied in this thesis. To overcome the issues of conventional couplers, a novel compact quadrature hybrid using the lumped elements is presented in this thesis. The proposed topology enables significant circuit size reduction further and provides a wider bandwidth in comparison with former approaches. The characteristics of the proposed topology could be analyzed by means of the transmission (ABCD) matrix method and was fabricated successfully on PCB and a Ka band balanced third-LO SHM MMIC, which could decreased the frequency of LO from Ku band to X band compared conventionally SHM topology. In addition, compact 90° and 180° hybrid couplers with harmonic suppression using lumped element band stop resonators are presented further. Experimental results reveal that two symmetrical couplers fabricated on PCB
suppressed the second harmonic below 26 dB and 30 dB, respectively, within the 0.6 dB amplitude imbalance and 2° phase error at 2.45GHz. To improve performance of CMOS VCOs further, three novel topologies are developed in this thesis. First, a common-source PMOS single-end VCO using 90nm CMOS technology is demonstrated. The topology results negative resistance by the drain inductance and the parasitic capacitance feedback path. The fabricated 1.75GHz VCO consumes 5.54 mW with a low supply voltage of 1 V. Second, a technique of the bottom series PMOS cross-coupled current source is presented to minimize the current noise source up-converted into phase noise. A 5 GHz differential Colpitts VCO employing the technique achieves a good phase noise of -100.3 dBc/Hz @100kHz. Finally, a Colpitts VCO using the technique of gate inductive feedback is demonstrated to relax the start-up condition. The proposed topology enhances the negative conductance and improves the power consumption further. As proof of the concept, a 7.9GHz full PMOS Colpitts VCO with a power consumption of 4.9 mW was implemented.

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