簡易檢索 / 詳目顯示

研究生: 吳炫德
Wu, Xuan-De
論文名稱: 同質性多核心系統下考慮資料傳遞和頻率切換延遲對任務及電壓做快速排程且節省能量的演算法
Fast and Energy-Aware Inter-Task and Voltage Scheduling considering Time Penalty of Frequency Switch and Data transmission for Real Time Homogeneous Multi-Processor Systems
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系碩士在職專班
Department of Electrical Engineering (on the job class)
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 63
中文關鍵詞: 動態電壓頻率調整嵌入式即時系統
外文關鍵詞: Dynamic Voltage Frequency Scaling (DVFS), Embedded Real Time System
相關次數: 點閱:94下載:4
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近來由於科技的進步,單一晶片上電晶體數目愈來愈多,而且在單一晶片內的核心也愈來愈多,並且將此技術應用在手攜式行動置上,而手攜式裝置皆是以電池供應能量,所以減少手攜式行動裝置的能量消耗才能延長使用時間。而動態電壓頻率調整己經被證明能有效的減少能量損耗,無論是在單處理器系統或是在多處理器系統。有別於之前的文獻採用進化演算法(Evolution algorithm )求得較佳的任務對映到處理器,再利用動態電壓頻率調整來降低能量損耗。因基因演算法找解必須花費較長的時間,所以我們嘗試將任務對映到處理器和指定任務的執行頻率同時處理,以期能更快速的找出解,同時我們加入了頻率切換和資料傳遞的時間損耗。
    實驗結果顯示,我們所提出的方法和Gradient-based scheduling algorithm比較,我們求得解的時間快了約4848倍,雖然能量消耗高出約8.19%。而有動態電壓頻率調整比沒有動態電壓頻率調整的能量節省約9.81%,其執行時間也僅需約0.5毫秒。同時也証明了頻率切換和資料傳遞的時間損耗確實會對能量損耗造成產生影響

    The advancement in semiconductor manufacturing technology has enabled more and more transistors to be integrated into a single chip. Processors with multi-cores integrated has been developed and become widely used in the consumer market for faster computing power. However, with the increasing number of transistors inside the chip, the power consumption has become an important issue to be tackled during the design stage, especially when the chip is used in portable electronic devices that powered by battery.
    Dynamic Voltage Frequency Scaling (DVFS) technique had been proven to effectively reduce the power consumption for the single processor and multi-processors system. Most of the works published so far are using DVFS to optimize the power consumption by first mapping the workload to operational unit using Evolution algorithm. However, to obtain the optimize solution using Evolution algorithm required a relatively long time. In this thesis, we present a new method by processing the mapping of workload to the operational unit and assigning the operating frequency at the same time. We have also added in the time penalty of frequency switching and data transfer into the algorithm in order to improve the precision.
    When compared with Evolution algorithm, our algorithm can generate a schedule which consumes the energy 8.19% more, but the execution time is about 4848 times faster. A total power savings of 9.81% could be achieved for the system employing DVFS and the overall processing time is only 0.5 milliseconds. This also proves that the time penalty of frequency switching and data transfer are contributing to the power consumption of the whole system.

    圖目錄………………………………………………………………………………iii 表目錄………………………………………………………………………………vii 第1章 緒論…………………………………………………………………………1 1.1 動機…………………………………………………………………………1 1.2 論文架構……………………………………………………………………2 1.3 貢獻…………………………………………………………………………3 第2章 相關背景……………………………………………………………………4 2.0嵌入式系統……………………………………………………………………4 2.1多核系統與連接架構…………………………………………………………4 2.2 功率消耗來源…………………………………………………………………5 2.3 動態電壓頻率調整介紹………………………………………………………6 第3章 相關工作與文獻探討………………………………………………………7 3.1 單核心系統DVFS lgorithm…………………………………………………7 3.1.1 Inter-task DVFS………………………………………………………7 3.1.2 Intra-task DVFS……………………………………………………13 3.1.3 Integrated task DVFS……………………………………………18 3.2 多核心系統 DVFS algorithm………………………………………………23 第4章 提出方法 …………………………………………………………………31 4.1 定義問題 …………………………………………………………………31 4.1.1 系統模組 ………………………………………………………………31 4.1.2 功率模組 ………………………………………………………………31 4.2 提出的方法 ………………………………………………………………33 4.3 任務重新排列…………………………………………………………… 34 4.4 任務對映到處理器 ………………………………………………………36 4.5 設定任務的頻率(assign frequency to task)…………………………36 4.6 範例說明 …………………………………………………………………39 第5章 實驗結果與分析 ……………………………………………………………43 5.1 模擬環境及條件限制 ……………………………………………………43 5.2 模擬結果比較………………………………………………………………44 5.3 資料傳遞延遲和頻率切換延遲對能量的影響…………………………47 5.4 處理器數目不同下的影響 ……………………………………………51 第6章 結論與未來展望 …………………………………………………………54 6.1 結論 ………………………………………………………………………54 6.2 展望未來 …………………………………………………………………54 6.3 參考文獻 …………………………………………………………………55

    [1] A.P. Chandrakasan, S. Sheng and R.W. Broderson, "Low power CMOS digital design," IEEE J. of Solid-State Circuits, vol. 27, no. 4, pp.473–484, Apr. 1992.
    [2] C. L. Liu and J. W. Layland, "Scheduling algorithms for multiprogramming in a hard real-time environment," J. of the Association for Computing Machinery, Vol. 20, No. 1, pp. 46-61, Jan. 1973.
    [3] J. E. Becker, C. Bieser, J. Becker, and K.-D. Mueller-Glaser, "Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System," in Proc. IEEE International Symposium on Industrial Electronics, vol.4, pp.3184-3189, Jul. 2006.
    [4] P. Pillai and K. G. Shin, "Real-time dynamic voltage scaling for low-power embedded operating systems," in Proc. 18th ACM Symposium on Operating Systems Principles, pp. 89-102, Oct. 2001.
    [5] D. Shin and J. kim, "A profile-based energy-efficient intra-task voltage scheduling algorithm for hard real-time applications," in Proc. International Symposium on Low Power Electronics and Design, pp.271-274, Aug. 2001.
    [6] M. P. Vestias, and H. C. Neto, "Co-synthesis of a configurable SoC platform based on a network on chip architecture," in Proc. Asia and South Pacific Conference on Design Automation, pp.48-53, Jan. 2006.
    [7] D. Shin, J. Kim and S. Lee, "Intra-task voltage scheduling for low-energy hard real-time applications," in Proc. IEEE Design & Test of Computers, vol.18, no.2, pp.20-30, Mar.-Apr. 2001.
    [8] T. Kim, "Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling," in Proc. 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp.199-206, Aug. 2006.
    [9] J. Seo, T. Kim and J. Lee, "Optimal intra-task dynamic voltage-scaling technique and its practical extensions," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.25, no.1, pp. 47- 57, Jan. 2006.
    [10] R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: task graphs for free," in Proc. the Sixth International Workshop on Hardware/Software Co-design, pp.97-101, Mar 1998.
    [11] L. K. Goh, B. Veeravalli, and S. Viswanathan, "Design of Fast and Efficient Energy-Aware Gradient-Based Scheduling Algorithms Heterogeneous Embedded Multiprocessor Systems," IEEE Trans. Parallel and Distributed Systems, vol.20, no.1, pp.1-12, Jan. 2009.
    [12] W. Y. Lee, "Energy-efficient Scheduling of Periodic Real-time Tasks on Lightly Loaded Multi-core Processors," IEEE Trans. Parallel and Distributed Systems, vol. PP, no.99, pp.1-17, 2011.
    [13] H. Aydin, Q. Yang, "Energy-aware partitioning for multiprocessor real-time systems," in Proc. International Parallel and Distributed Processing Symposium, pp. 9, Apr. 2003.
    [14] J.-J. Chen, T.-W. Kuo, "Energy-Efficient Scheduling of periodic Real-Time Tasks over Homogeneous Multiprocessors," in Proc. Real-Time and Embedded Technology and Applications Symposium, pp.30-35, Apr. 2008.
    [15] P. Malani, P. Mukre, Q. Qiu and Q. Wu, "Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload," in Proc. Design, Automation and Test in Europe, pp.652-657, Mar. 2008.
    [16] M.T. Schmitz and B.M. Al-Hashimi, "Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems," in Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.514-521, 2002.
    [17] C. Xian, Y.-H. Lu, and Z. Li, "Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time," in Proc. 44th ACM/IEEE Design Automation Conference, pp.664-669, Jun. 2007.
    [18] C. Xian, Y.-H. Lu, and Z. Li, "Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.8, pp.1467-1478, Aug. 2008.
    [19] H.-Y. Lin, "Aggressive Look-Ahead Earliest Deadline First algorithm for Power-Aware Embedded Real-Time Systems," in Department of Electric Engineering Thesis for Master of Science, National Cheng-Kung University, Tainan, Taiwan, 2006.

    下載圖示 校內:2016-09-08公開
    校外:2016-09-08公開
    QR CODE