電路可靠度一直都是超大型積體電路重要的觀念。其中負偏壓溫度不穩定性 (Negative Bias Temperature Instability NBTI) 隨著製程的進度，漸漸成為可靠度考量的主要因素之一。NBTI可能會受到運作環境的影響，例如Signal Probability、溫度以及電壓，使得電路在運作一段時間後，會降低PMOS運作速度，導致整體電路的效能衰退或稱為老化，在分析電路可靠度時，是一個極大的挑戰。另外一項電路設計的主要考量是節省漏電流 (Leakage power) 的消耗電量。在此論文中，我們提出了一個完整的分析以及最佳化流程，結合了NBTI的靜態時序分析(NBTI-Aware Static Timing Analysis) 可以有效的指出必須改良的電路位置以及改良的先後順序，有利於使用各種技巧來降低NBTI老化的現象。因此我們基於使用傳輸閘 (Transmission gate) 的概念，提出了一套新的演算法設計，用來降低NBTI老化的現象，同時也降低漏電流的消耗。這個方法與Gate Replacement的方法相比，有極高的彈性，可以適用於各種電路分析當中。從實驗數據可以得知，相較於Gate Replacement的方法，我們提出的新方法在節省相同的漏電流下，平均可以多改善2.44倍的NBTI老化現象，而最高可以比Gate Replacement多改善到20倍的效果。整體來說，此方法伴隨著增加19%面積的代價，平均可以節省19.39%的漏電流以及改善36.56%的NBTI老化現象。

Circuit reliability has been one of the major concepts in VLSI circuits and system designs. As technology advances, NBTI (Negative Bias Temperature Instability) has gradually become one of the main factors for estimating reliability. NBTI is affected by the operating environment such as signal probability, temperature and supply voltage, and this, after operating for a period of time, will reduce the switching speed of PMOS transistors and cause temporal performance degradation. In analysis circuit reliability, this is indeed a great challenge. Another main concern for circuit designs is to reduce leakage consumption. In this thesis, we put forward a complete analysis, process, and combine NBTI-Aware Static Timing Analysis, which can efficiently point out the circuit location to be improved and the order that needs improving. And this is beneficial in reducing the aging phenomena of NBTI with various techniques. Therefore, based on the concept of using transmission gate, we propose a novel transmission gate-based technique, which has higher flexibility and efficiency, to optimize NBTI-induced degradation and leakage. Compared to the gate replacement technique, our simulation results show that our proposed technique has up to 20X and 2.44X on average improvement on NBTI-induced degradation with comparable leakage power reduction. With 19% area penalty, combining our technique with the gate replacement can reduce 19.39% of the total leakage power and 36.56% of NBTI-induced circuit degradation.

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