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研究生: 林資濱
Lin, Tz-Bin
論文名稱: 底部填膠材料體積收縮行為之研究與量測
Study and Measurement of Volume Shrinkage for Underfill Encapsulants
指導教授: 李輝煌
Lee, Huei-Huang
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 76
中文關鍵詞: P-V-T-C關係式熟化收縮底部填膠材料覆晶封裝
外文關鍵詞: P-T-V-C equation, underfill encapsulant, cured-induced shrinkage
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  • 在覆晶(Flip-chip, FC)封裝技術朝向輕薄短小兼具高性能的趨勢下,底部填膠材料(underfill encapsulants)的各項性質對於封裝產品的影響大幅提昇。然而,過去對於覆晶封裝元件的模擬,僅考慮不同材料間的熱膨脹係數(Coefficient of Thermal Expansion, CTE)差異所造成的翹曲(warpage),而忽略了底部填膠材料熟化收縮(cured-induced shrinkage)所造成的翹曲量,往往無法準確估計出封裝產品的內應力分佈與翹曲型態,進而無法準確估計成品的可靠度。
    本論文利用熱分析儀配合統計技巧,建立出底部填膠材料的P-V-T-C(Pressure-Volume-Temperature-Cure)關係式,此關係式可用來描述壓力、體積、溫度、熟化度四者間的關係,藉以掌握熟化過程中材料的體積收縮量進程,使得熱收縮與熟化收縮效應能在IC封裝的分析中同時考慮。

    Plastic packaging in the electronic industry has been popular during the past decades. As a result of the flip chip technology is inclined to be light and high density, the material properties of underfill encapsulant have made a great impact on plastic package. In general, different coefficients of thermal expansion (CTE) values of constituted materials are considered as the main cause of warpage. Accordingly, in the past years, the cure-induced volume shrinkage is neglected in warpage simulation. However, in recent years, there are more and more evidences showing that it is not sufficient to predict the amount of warpage if considering only the CTE values of different component materials in a package. Therefore, the cure effect and the thermal effect are both considered in this research.
    In this study, the P-V-T-C equation of underfill encapsulant is developed by employing the thermal analyzer and statistical technique. The relations between the pressure, volume, temperature and conversion (degree of cure) can be expressed by the P-V-T-C equation. By way of the P-V-T-C equation, the volume shrinkage of underfill encapsulant can be calculated. Consequently, both the cure and thermal effects can be involved in various analyses of IC packaging.

    摘 要 I Abstract II 致 謝 III 目 錄 V 表 目 錄 VII 圖 目 錄 VIII 符 號 說 明 XII 第一章 緒論 1 1-1 前言 1 1-2 IC封裝的演進 1 1-3研究目的 10 1-4 文獻回顧 11 第二章 理論分析 15 2-1 熟化反應動力學模式 15 2-2 P-V-T-C關係式 19 第三章 實驗方法 22 3-1 實驗目的 22 3-2 實驗規劃 22 3-3 實驗設備 23 3-3-1 底部填膠材料 23 3-3-2 DSC 24 3-3-3 TMA 25 3-4 實驗步驟 25 第四章 實驗結果 26 4-1 底部填膠材料熟化反應動力學模式 26 4-2 底部填膠材料熟化體積收縮量測 43 4-3 P-V-T-C關係式之建立 53 第五章 結論與展望 68 參考文獻 70 索引 75 自述 76

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