此篇論文提出一個新穎的測試架構結合了掃描測試與自我測試兩者的優點。主要概念為將待測試電路所需之測試壓縮資料記錄(儲存)於新穎的掃描鏈架構，並在測試時透過萃取與解壓縮儲存資料以提供待測試電路測試資料。這樣的概念需要相當高測試壓縮率之測試壓縮技術，使測試壓縮資料量小於待測試電路中掃描原件總數，方能儲存所有測試壓縮資料於待測試電路中。為了達到高測試壓縮率，論文提出一創新壓縮技術，此技術結合廣播式掃描之概念，並僅使用單一輸入腳位提供測試壓縮資料。在此論文亦導入切割掃描鏈與鎖住時脈訊號之概念於測試架構中使測試流程夠有效率，同時也降低測試時的功率消耗，此外，此測試架構包含晶片內測試控制器可以自動產生配合測試流程的控制訊號，藉此大幅度降低或甚至去除測試機台需求與相對應的測試成本。實驗結果顯示，在一個8個核心的多核心電路，電路大小約為570萬個邏輯匝數的 OpenSPARC T2，此技術僅使用此待測電路中59.4%的掃描原件(儲存空間)，儲存針對定值錯誤所需之所有測試壓縮資料且保有100%測試覆蓋率。雖然在此研究，主要研究對象為定值錯誤，然而在處理不同錯誤模式、錯誤偵測以及工程變更(ECO)，也有在此論文中探討著。

This thesis presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain structure, and extract and decompress them during testing. This requires a very high compression ratio to obtain a low test data volume (TDV) that is smaller than the number of scan cells in the circuit under test. To achieve such a high compression ratio, we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture. We also utilize the concept of scan chain partitioning and clock gating to increase the efficiency of the test flow in our test architecture. An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external ATE. Experimental results on the 8-core open-source OpenSPARC T2 processor with 5.7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59.4% of the scan cells of the processor. Though this work is mainly for the testing of stuck-at faults, extensions to deal with more fault models, fault diagnosis, and engineering change orders (ECO) are also discussed.

[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, Ch. 5, 2006.
[2] L.-T. Wang, C. E. Stroud and N. A. Touba, System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, Ch.2, 2010.
[3] N. A. Touba, “Survey of test vector compression techniques, ”IEEE Trans. on Design & Test of Computers.,vol. 23, no. 4, pp.294 -303, 2006.
[4] K.-J. Lee, J.-J. Chen and C.-H. Huang, “Using a Single Input to Support Multiple Scan Chains,” in Proc. Int',l Conf. Comput.-Aided Design, 1998, pp. 74-78.
[5] J. Rajski, J. Tyszer , M. Kassab and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. on Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 5, pp. 776-792, 2004.
[6] U. S. Mehta, K. S. Dasgupta and N. M. Devashrayee, Code Based Test Data Compression for SoC Testing: Optimization of Time, Power and Area Overhead, LAP LAMBERT Academic Publishing, 2012.
[7] J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, and M. Kassab, “X-Press Compactor for 1000x Reduction of Test Data,” in Proc. Int'l Test Conf., 2006, paper 18.1.
[8] B. Koenemann, “LFSR-coded test pattern for scan designs,” in Proc. Eur. Test Conf., 1991, pp. 237–242.
[9] S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of vector patterns through reseeding of multiple polynomial linear feedback shift register,” in Proc. Int'l Test Conf., 1992, pp.120-129.
[10] B. Koenemann, C. Barnhart, B. Keller, T. Snethen; O. Farnsworth, D. Wheater, “A SmartBIST Variant with Guaranteed Encoding,” in Proc. Asian Test Symp., 2001, pp. 325-330.
[11] L. Li and K. Chakrabarty, “Test set embedding for deterministic BIST using a reconfigurable interconnection network,” IEEE Trans. on Comput.-Aided Design of Integr. Circuits and Syst., vol. 23, no. 9, pp. 1289-1305, 2004.
[12] G. Kiefer, H. Vranken, E.J. Marinessen and H.-J. Wunderlich, “Application of deterministic logic BIST on industrial circuits,” Journal of Electronic Testing: Theory and Applications, vol. 17, pp. 351-362, 2001.
[13] A.-W. Hakmi, S. Holst, H.-J. Wunderlich, Jü. Schlöffel, F. Hapke and A. Glowatz, “Restrict Encoding for Mixed-Mode BIST,” in Proc. VLSI Test Sympo., 2009, pp. 179-184.
[14] M. A. Kochte, C. G. Zoellin and H. J. Wunderlich, “Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead,” in Proc. Eur. Test Symp., 2009, pp. 53-58.
[15] Y. Li, S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns," in Proc. Design Automa. and Test in Eur., 2008, pp. 885-890.
[16] D. Xiang, X. Wen and L. T. Wang, "Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding," IEEE Trans on Very Large Scale Integration (VLSI) Syst, vol. 25, no. 3, pp. 942-953, 2017
[17] D. Xiang, K. Chakrabarty and H. Fujiwara, "Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip," IEEE Trans on Computers, vol. 65, no. 9, pp. 2767-2779, 2016.
[18] K. J. Lee, P. H. Tang and M. A. Kochte, "An on-chip self-test architecture with test patterns recorded in scan chains," in Proc. Int'l. Test Conf., 2016, pp. 1-10.
[19] J. Z. Chen, K. J. Lee, “Test Stimulus Compression Based on Broadcast Scan with One Single Input,” IEEE Trans on Comput-Aided Design of Integr Circuits and Syst., vol. 36, no. 1, pp.184-197, 2017
[20] RotorCPU, Jeff Bush.
https://github.com/jbush001/RotorCPU/wiki
[21] OpenSPARC T2, Oracle Inc.
http://www.oracle.com/technetwork/systems/opensparc/index.html.
[22] F. Yang, S. Chakravarty, N. Devta-Prasanna, S. M. Reddy and I. Pomeranz, "Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells," in Proc. Int’l Symp. Defect and Fault Tolerance of VLSI Systems, 2008, pp. 394-402.
[23] Mentor. Inc., Tessent Testkompress User Guide, Version v9_3.
[24] Synopsys Inc., TetraMAX ATPG User Guide, Version L-2016.03.
[25] I. Hamzaoglu and J. H. Patel, "Reducing test application time for full scan embedded cores," in Proc Int'l Symp on Fault-Tolerant Computing (FTCS), 1999, pp. 260-267.
[26] G. Giles, J. Wang, A. Sehgal, K. J. Balakrishnan, and J. Wingfield, “Test access mechanism for multiple identical cores,” in Proc. Int'l. Test Conf., 2009, pp. 1-10.