| 研究生: |
謝其昌 Hsieh, Chi-Chang |
|---|---|
| 論文名稱: |
矽穿孔結構熱應力對矽晶反轉層移動率之影響 Analysis of Through-Silicon Via Thermal Stresses Induced Mobility Change in Silicon Inversion Layer |
| 指導教授: |
屈子正
Chiu, Tz-Cheng |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 機械工程學系 Department of Mechanical Engineering |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 中文 |
| 論文頁數: | 141 |
| 中文關鍵詞: | 直通矽穿孔 、矽晶反轉層 、移動率 、熱應力 |
| 外文關鍵詞: | TSV, inversion layers, mobility, thermal stress |
| 相關次數: | 點閱:73 下載:5 |
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直通矽穿孔(through silicon via;TSV)三維積體電路已成為提高設備密度和開發系統及封裝解決方案的主要技術之一,TSV結構面臨一個關鍵問題是銅柱與矽基板的熱膨脹係數差異太大,造成材料的不匹配,而產生熱應力。熱應力對TSV結構電性的影響,我們可以由熱應力對矽晶反轉層引起的電子或電洞移動率的變化觀察到。
本研究是用數值方法模擬TSV銅柱周圍的應力集中現象,估計在n-MOSFET與p-MOSFET矽晶反轉層載子移動率的影響。首先利用有限元素分析矽在(001)表面,有TSV結構的矽芯片與沒有TSV結構的矽芯片應力差異。再來把矽的應力變化帶入壓阻公式,計算延著通道路徑方向載子移動率的變化。然後比較應變矽與非應變矽,延著通道<100>晶格方向或<110>晶格方向結果。我們也考慮改變幾何尺寸,如TSV直徑,銅柱的間距,和矽晶厚度,比較移動率的變化。最後我們有以一個更逼真的有封膠3D堆疊芯片模型進行分析。探討TSV晶片角落位置,應力對載子移動率的影響。透過研究結果,我們定義一個排除區在TSV銅柱周圍,以做為未來設計規則。
Three-dimensional (3D) integration using through-silicon via (TSV) has emerged as one of the primary technologies for increasing device density and developing system-in-package solutions. A critical concern for TSV is the thermal stress developed in the 3D structure as a result of the significant difference in the coefficients of thermal expansions (CTE) between the Cu via and the Si substrate. The influence of the TSV-related thermal stress on the electrical characteristics may be considered by the thermal stress-induced electron or hole mobility changes in the Si inversion layer.
In this study, effects of stress concentration around Cu TSV on carrier mobility in n-MOSFET and p-MOSFET Si inversion layers were estimated by using numerical simulations. Finite element analyses were first performed to determine the difference in stress state on the (001) Si surface when the Si die is changed from a configuration without TSV to one with TSV. The changes of stresses were then substituted into piezoresistance equations for silicon to determine carrier mobility changes along the channel directions. Results were obtained for transistors with channels either along <100> or <110> direction, and for devices fabricated with either strained-Si or unstrained-Si technology. Geometrical factors such as through-silicon via diameter, via pitch and die thickness on mobility were also considered. A more realistic model of a 3D-stacked die in an overmolded package was also analyzed to investigate the effect of TSV-die corner stress interaction on carrier mobility. Results of the study can be served as a basis for defining the keep-out dimension around the Cu TSV in layout design rules.
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