晶圓級封裝(wafer level package, WLP)相較於傳統製程封裝有較小尺寸、較佳電性及較低製造成本等優點，因此被廣泛應用於攜帶型電子產品。由於各材料間之熱膨脹係數(coefficient of thermal expansion, CTE)不匹配，錫球接點及銅佈線在溫度循環時承受的熱應力將導致其發生疲勞破壞。因此為提升WLP熱循環下之疲勞壽命，透過幾何參數之最佳化，並設計最佳化之參數後再以實驗驗證結果為目前電子封裝研發之趨勢。
本文針對WLP進行以二次反應曲面(quadratic response surface)及有限元素模型之結構最佳化。考慮之設計參數包括銅墊片直徑及介電薄膜厚度，並利用全因子設計法(full factorial design)規劃參數之實驗配置。其中以三維之非線性有限元素計算錫球之塑性功循環增量及銅佈線之塑性應變範圍作為WLP疲勞壽命之損傷指標。為了考慮在尺寸參數之製程公差及疲勞試驗數據不足的情況，採用結合性能指標法(performance measure approach, PMA)之可靠度設計最佳化(reliability-based design optimization, RBDO)進行計算，並分別以損傷指標及疲勞壽命為目標函數，搜尋提升WLP結構可靠度之最佳參數組合。
本研究所得之結果可作為改進WLP結構可靠度參考，並可將所使用之系統化流程延伸應用於其他電子產品之疲勞壽命評估。

In wafer level packages (WLPs), fatigue crackings in solder joints and the redistribution layer (RDL) Cu traces are likely to occur under temperature cycling because of the mismatch in the coefficients of thermal expansion (CTEs) between package constituents. An important task in developing WLP technology is therefore to perform structural optimization for improving temperature cycling reliability. In this thesis, reliability optimizations of WLP by using quadratic response surface and finite element (FE) model are presented. Design variables including RDL Cu pad diameter, pad opening diameter and polymer dielectric thickness are considered. Damage indices including inelastic strain energy density and equivalent plastic strain increments are obtained by using numerical FE simulation to assess the fatigue life. For the response surface based analysis, a 3-level full factorial design is applied for constructing the response model. Uncertainties including manufacturing process tolerances and fatigue life distributions are considered in the analyses. By using either the damage indices or failure life as the objective function, a reliability-based design optimization (RBDO) with performance measure approach (PMA) is applied for determining the optimal interconnect geometry design for WLP.

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