覆晶晶粒尺寸封裝(FCCSP)與一般傳統打線接合的構裝方式不同，係由晶片直接以凸塊焊球(Solder Bump)連接基板，由於覆晶封裝具有良好電氣特性、高I/O接點密度，且能縮小IC尺寸增加每片晶圓產出，故較傳統封裝型態更適用於高速、高電流與高腳數等高階電子元件產品。本文針對覆晶晶粒尺寸封裝在溫度循環負荷下，利用有限元素分析軟體模擬錫球之變形行為，以瞭解錫球之疲勞壽命。

　　首先以Surface Evolver求出錫球迴焊後之形狀，再將形狀因子導入ANSYS分析軟體進行分析。其材質選用共晶(Eutectic)無鉛錫球含96.5Sn3.5Ag之FCCSP封裝模式，建構在FR-4電路板上，並以葛拉佛拉-阿瑞尼阿斯潛變模式(Garofalo-Arrhenius Creep)表示 ，配合有限元素分析法ANSYS 7.0之軟體在三維模型下，探討五種FCCSP封裝模型在-20℃~110℃溫度循環下，最外側錫球之疲勞壽命。這五種模型為原設計模型、模型基板為BT-Resin、模型基板為High-α Ceramics、模型封膠為Mold Resin及模型封膠為Potting Resin等。

　　最後使用田口式方法，討論基板厚度、錫球墊半徑、底膠彈性模數、底膠線膨脹係數、基板彈性模數、基板線膨脹係數、FR4彈性模數及FR4線膨脹係數等，各控制因子之間互動對錫球疲勞壽命之影響，並找出最佳之水準組合，以提升構裝體中錫球之疲勞壽命。

　　The flip chip chip scale package (FCCSP) is different from conventional wire-bonding package by flipping the silicon chip over and connecting the solder bumps to the substrate directly. Because the flip chip package has excellent electrical properties, high I/O density, and yield-increase of each wafer by reducing the size of IC, therefore, it is more suitable to those advanced electronic products demanding high speed, large electric current, high-pin-count than other traditional packages. This paper focuses on the fatigue life of the solder joint in FCCSP under thermal cycling loads, and the finite element analysis software is applied to simulate the deformation of solder balls.

　　First, Surface Evolver is applied to predict the shape of solder joints after reflow, then the results are brought into ANSYS as the shape factors to simulate the fatigue life of the solder joint in the FCCSP. This research focused on the FCCSP with eutectic lead-free 96.5Sn3.5Ag solder joints on FR-4 PCB, and adopted Garofalo-Arrhenius creep model along with finite element software, ANSYS 7.0, to investigate the outer solder fatigue lives of five FCCSP models in three-dimension under thermal cycling of -20℃~110℃. These five models are the original model, the model with BT-resin substrate, the model with high-α ceramics substrate, the model with BT-Resin substrate, the model with Mold-resin encapsulant, the model with Potting-resin encapsulant.

　　Finally, Taguchi method is used to study the effect of designing parameters, such as substrate thickness, solder pad radius, Young’s modulus of underfill, linear coefficient of expansion of underfill, Young’s modulus of FR4, linear coefficient of expansion of FR4, on the fatigue life of the solder joint. Consequently, the optimal combination of factor-level is attained, and hopefully to improve the fatigue life of solder joints in the packaging.

[1] 林柏寬, “助焊劑裂解產生之氣泡對無鉛錫球構裝體影響之研究”, 國立中正大學機械研究所碩士論文,2003.
[2] 郭昱綸, “覆晶球陣列電子封裝在溫度循環下的熱應力與熱應變分析”,國立中山大學機械與機電工程研究所碩士論文,2000.
[3] L. S. Goldmann, “Geometric Optimization of Controlled Collapse Interconnection”, IBM Journal of Research and Development, vol. 120, pp. 175-178, May 1969.
[4] A. Metrol, “Application of the Taguchi Method on the Robust Design of Molded 225 Plastic Ball Grid Array Packages”, IEEE Transactions on Components, Packaging and Manufacturing Technology Part B, pp. 734-743, 1995.
[5] S. M. Heinrich, M. Schaefer, S. A. Schroeder, P. S. Lee, “Prediction of Solder Joint Geometry in Array-Type Interconnections”, ASME J. Elec. Pack., Vol. 118, No. 3, pp. 114-121, 1996.
[6] K. N. Chiang, W. L. Chen, “Electric Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array”, ASME J. Elec. Pack., Vol. 120, pp. 175-178, 1998.
[7] L. Mercado, Vijay Sarihan, Yifan Guo, and Andrew Mawer, “Impact of Solder Pad Size on Solder Joint Reliability in Flip Chip PBGA Packages”, IEEE Transactions on Advanced Packaging, Vol. 23, No. 3, Aug. 2000.
[8] A. Metrol, “Application of the Taguchi Method to Chip Scale Package(CSP) Design”, IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 266-266, 2000.
[9] K. N. Chiang, C. A. Yuan, “An Overview of Solder Bump Shape Prediction Algorithms with Validations”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 2, pp. 158-162, May 2001.
[10] J. H. L. Pang, D. Y. R. Chong, “Flip Chip on Board Solder Joint Reliability Analysis Using 2-D and 3-D FEA Models”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 4, pp. 499-506, 2001.
[11] L. Cergel, L. Wetz, B. Keser, J. White, “Chip Size Packages with Wafer-Level Ball Attach and their reliability”, Smolenice Castle, Slovakia”, pp. 14-16, Oct. 2002.
[12] J. Li, and S. Yi, “Studies on Thermal Mechanical Properties of PBGA Substrate and Material Construction”, 2002 Electronic Component and Technology Conference, pp. 1595-1604, 2002.
[13] Cristina Anderson, Zhonghe Lai, Johan Liu, Hairong Jiang, Yongning Yu, “Comparison of Isothermal Mechanical Fatigue Properties of Lead-Free Solder Joints and Bulk Solders”, ICEPT, pp. 371-376, 2003.
[14] L. Anand, “Constitutive Equations for the Rate-Dependent Deformation of Metals at Elevated Temperature,” Transactions of ASME, 12/Vol. 104, pp. 12-17, January 1982.
[15] ANSYS Menu, “Newton-Raphson Procedure”, ANSYS Theory Reference, Reversion5.5, pp. 15-28-40, 1998.
[16] S. Wiese, “Constitutive Behavior of Lead-free Solders vs. Lead-containing Solders -Experiments on Bulk Specimens and Flip-Chip Joints”, Electronic Components and Technology Conference, 2001.
[17] John H. Lau, “Modeling and Analysis of 96.5Sn-3.5Ag Lead-Free Solder Joints of Wafer Level Chip Scale package on Buildup Microvia Printed Circuit Board”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, No.1, pp. 51-58, January 2002.
﹝18﹞ANSYS Menu, “Structural Analysis User's Guide”.
﹝19﹞徐秉業, 劉信聲, “應用彈塑性力學”, 凡異出版社, 1997.
[20]萬政憲,“在熱循環作用下錫球結構與配置方式對PBGA構裝之可靠度探討,”成功大學工程科學系碩士畢業論文, 1999.
[21] ANSYS Menu, “Modeling and Meshing Guide/ Nonlinear Structural Analysis,” ANSYS 6.0, 8.3.1.1.1. Plastic Material Options.
[22] J. H. Lau and Shi-Wei R. Lee, “Chip Scale Package, CSP: Design, Materials, Processes, Reliability and Applications”, McGraw-Hill Companies, Inc. New York, 1999.
[23] L. F. Coffin, Jr., “A Study of Effects of Cyclic Thermal Stress on a Ductile Metal”, Trans. ASME, Vol. 76, pp. 931-950, 1954.
[24] W. Engelmaier, ”Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-6, No.3, pp. 52-57, 1983.
[25] H. D. Solomon, “Fatigue of Solder”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 9, No. 4, pp. 423-432, 1986.
[26] John H. L. Pang, “CBGA Solder Joint Reliability Evaluation Based on Elastic-Plastic-Creep Analysis”, Trans. ASME, Vol. 122, pp. 255-261, 2000.
[27] K. A. Brakke, “ Surface Evolver Manual ”, Minneapolis, MN: The GeometryCenter, 1994.
[28] Chiang K. N.,Yuan C. A., “An Overview of Solder Bump Shape Prediction Algorithms with Validations ”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 2, pp. 158-162, May 2001.
[29]李輝煌, “田口方法品質設計的原理與實務”,高立圖書有限公司,2000.
[30]劉振中, “無鉛錫球含多層金屬薄膜之晶圓級封裝結構應力分析”, 成功大學工程科學系碩士畢業論文, 2003.
[31]梁金條, “利用有限元素與田口方法探討FCCSP構裝無鉛錫球之最佳化疲勞壽命”, 成功大學工程科學系碩士畢業論文, 2006.
[32] D. R. J. Owen and E. Hinton, “Finite Elements in Plasticity: Theory and Practice”, Pineridge Press Limited, Swansea U.K., 1980.
[33] Morihiko Ikemizu, Yuji Fukuzawa, Jirou Nakano, Testuya Yokoi, Kenji Miyajima, Hiroshi Funakura, Eiichi Hosomi, “CSP Solder Ball Reliability”, IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1997.