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研究生: 朱國永
Chu, Kuo-Yung
論文名稱: 應用於格雷序列之時間同步器在無線開放式研究平台-WARP之效能評估及驗證
Evaluation and Verification of Timing Synchronizer for Golay Sequences on Wireless Open-Access Research Platform
指導教授: 卿文龍
Chin, Wen-Long
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 69
中文關鍵詞: 時間同步器格雷互補序列無線開放式研究平台
外文關鍵詞: Timing Synchronizer, Golay complement Sequences, Wireless Open-Access Research Platform
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  • 正交分頻多工(orthogonal frequency-division multiplexing, OFDM)已經是一成熟且應用廣泛的通訊技術,其中同步技術對於通訊演算法又極其關鍵。尤其是對OFDM傳輸技術而言,同步錯誤將會造成嚴重的符元間干擾(inter-symbol interference, ISI)及子載波間干擾(inter-carrier interference, ICI),而這些干擾將會嚴重影響後續通道等化(equalization)及資料解碼(decoding)的效能。
    近年來具特殊自相關特性之格雷序列(Golay sequences)常用來當作封包的前序(preamble),例如以IEEE 802.15.3c標準為基礎之Wireless HD技術,以及由WiGig聯盟(Wireless Gigabit Alliance)以現存IEEE 802.11標準為基礎所制定之WiGig規範。然而,使用傳統比對濾波器(matched-filter)之同步演算法,無法適用於使用格雷序列作為前序的時間同步器。
    據此,本研究利用本實驗室謝沂庭學姊在2013年所設計之時間同步演算法,進行系統的實現,目的在於評估以格雷序列作為前序之OFDM系統中真實環境下的效能表現。首先,為了將此時間同步演算法實現在系統平台上,我們將電路做些許的修改,並在暫存器轉移階層(register transfer level, RTL)建構基頻接收機,用以初步評估接收機時間同步演算法之效能表現,硬體實現層面會採用萊斯大學所開發的無線開放式研究平台(Wireless Open-Access Research Platform, WARP)實現本研究之硬體架構,評估在真實環境下的效能表現。

    Synchronization is critical in the design of an OFDM receiver. Large timing offsets result in a loss of orthogonality between subcarriers, ISI, and severe bit error degradation. To minimize this degradation, standards incorporate preambles intended for all OFDM acquisition functions including automatic gain control (AGC) and synchronization. However, the IEEE 802.11 specification adopts Golay sequences as the preambles, which have special autocorrelation properties. Accordingly, conventional synchronization algorithms using the matched filter cannot be applied in Golay sequences. To address this issue, this paper presents a design and implementation on timing synchronizer for Golay sequences. In order to improve the synchronization performances of OFDM systems, we propose a novel and efficient algorithm according to the special autocorrelation properties of Golay sequences. The performance is evaluated by the register-transfer-level (RTL) model which is implemented on FPGA. Finally, the hardware architecture is implemented and verified by Wireless Open-Access Research Platform.

    中文摘要................................i 英文摘要...............................ii 誌謝................................viii 目錄..................................ix 表目錄...............................xii 圖目錄..............................xiii 符號說明.............................xvii 第1章、 緒論............................1 1.1 前言 ..............................1 1.2 研究動機...........................2 1.3 論文架構...........................3 1.4 設計流程...........................4 第2章、 系統模型........................5 2.1 OFDM系統與IEEE 802.11a介紹..........5 2.1.1 OFDM系統.........................5 2.1.2 IEEE 802.11a實體層規格............6 2.2 格雷互補序列.......................10 2.2.1 格雷互補序列介紹..................10 2.2.2 非週期性自相關函數................11 2.3 系統架構..........................14 2.3.1 加入格雷序列之封包結構.............14 2.3.2 接收端系統模型...................16 2.4 通道模型..........................19 2.4.1 多重路徑通道模型..................19 2.4.2 可加性白色高斯雜訊................21 第3章、 時間同步演算法與硬體設計..........22 3.1 時間同步演算法 .....................22 3.2 模擬與分析.........................25 3.3 硬體設計..........................29 3.3.1 時間同步演算法電路................29 3.3.2 電路架構的改善...................41 第4章、 實驗環境與實驗結果...............46 4.1 WARP介紹..........................46 4.2 實現環境..........................48 4.2.1 模擬環境........................48 4.2.2 真實環境........................54 4.3 量測結果及效能分析..................61 第5章、 結論與未來展望..................67 參考文獻..............................68

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