在半導體製程中每一片晶粒(Die)都需要以晶圓針測中的探針卡(Probe card)進行針測。對於銲墊晶圓(Pad wafer)測試而言，透過探針卡之探針與晶粒上鋁銲墊(Al pad)的良好接觸，量出電路的電性，進而判斷出晶粒的好壞，然而不適當的探針設計及針測參數有可能造成銲墊的針痕(Scrub mark)過大及損傷銲墊問題，進而造成後續銲線製程的接觸不良問題，尤其是在進行高溫環境晶圓針測時，更是不易掌控針痕的位置及大小。另外，對於錫鉛凸塊晶圓(Solder bump wafer)測試而言，藉由垂直探針卡上之探針與晶粒上特定錫鉛凸塊的接觸，進行電氣性質測試。相較於傳統懸臂式探針卡，垂直式探針卡可因應高針數短針距的測試需求，其在電性測試上有更為優異的表現。而且垂直探針卡更具有容易更換，可執行陣列的微細間距(Area array)針測的優勢。垂直式探針和錫鉛凸塊的接觸問題，是晶圓測試的成敗關鍵，不適當的垂直探針設計及針測參數會使錫鉛凸塊壓痕過大，進而造成後續封裝製程的良率及可靠度問題。
本研究中進行多種探針幾何外型與不同針測行程之晶圓針測實驗，並建立出完整的實驗結果。此外建立有限元素分析模型來進行晶圓針測模擬，利用3D的模型來模擬銲墊及錫鉛凸塊晶圓的受力與探針的力學行為，針對探針尺寸及針測行程(Overdrive)之間的關係加以探討，將之結果與實驗做比較，藉由此方法可以了解探針的幾何參數的選擇對銲墊刮痕及錫鉛凸塊壓痕的影響，此研究成果可以提供探針卡設計之幾何參數選擇與求得最佳的針測參數。探針理論方析方面，利用卡氏定理(Castigliano’s Theorem)來探討探針接觸力與行程之間的關係，利用此模型可有效的預測探針於不同針測參數時所可能產生的針痕大小，針對不同針測產品找出對應的最佳化探針，避免產生銲墊及錫鉛凸塊受損之問題。針對高溫環境下銲墊晶圓測試問題，在本文中藉由田口方法的導入找出最佳的高溫針測參數，來改善高溫環境針測時銲墊損傷問題。
最後將晶圓測試之有限元素模型模擬，與實驗及理論結果作比較，驗證有限元素模型及理論分析可以用於描述真實之晶圓針測過程，藉此可以用來模擬及預測不同針測參數及探針尺寸所產生之針痕，並建立出不同針測參數之完整數據，找出最佳的測試參數，以期降低銲墊及錫鉛凸塊損傷風險。

Certainly, wafer probing technique is important for testing the functionality of IC (Integrate Circuit) devices. For safety of Al (Aluminum) pad wafer, the cantilever needle card must be examined to realize the performance before the on-line testing to prevent the phenomena of the pad edge excursion and the excessive scrub length during bonding pad wafer testing, particularly for high temperature probing. On the other hand, in terms of solder bump wafer testing, the vertical probe card is a reliable solution to satisfy requirements of fine pitch and area array bumps. Indeed, unsuitable probing recipe could cause seriously bump height variation, unacceptable probe mark area and many further chip assembly problems. For these reasons, a complete contact model of solder bump products during wafer probing is established and discussed.
In order to avoid bonding pad and solder bump damage, the finite element method, which is developed for analyzing the probing behavior during pad and bump wafer testing, predict the probing mark in this thesis. Moreover, a simple and accurate theoretical analysis is established for rapidly designing an appropriate probing system for bonding pad and solder bump wafer probing. In this thesis, the Taguchi method and variance analysis are used to conducted optimal recipes for the cantilever probing needle with respect to the ideal scrub length in high temperature environments. Furthermore, the mechanism of pad and bump wafer probing are investigated to derive the relationships among the contact force, overdrive, probe geometry, material properties, and scrub mark area are derived. The results, which are further determined by using the theoretical analysis, the finite element method and the experiment, are consistent. In addition, the pad and bump wafer probing criteria are discussed to avoid bonding pad and solder bump damage. Finally, the effects of various parameters on the probing behavior are investigated and optimized.

[1] Micronics Japan co., Inc. (2011). Available:http://www.mjc.co.jp/eng/product/ index3_1.html.
[2] S. Maekawa, M. Takemoto, Y. Deguchi, K. Miki & T. Nagate, “Highly reliable probe card for wafer testing,” in Proc. of IEEE Electronic Components and Technology Conference, pp. 1152-1156, 2000.
[3] D. Krzysztof, “Advances in Conventional Cantilever Probe Card”, in Proc. of the International Conference IEEE SouthWest Test WorkShop, pp. 1-28, 2003.
[4] B. Mariner, “Probe Market Overview by VLSI Research,” in Proc. of the International Conference IEEE SouthWest Test WorkShop, 2005.
[5] L. Tran & R. Rincon, “Why using finite element analyses to optimize cantilever probe card design”, in Proc. of the International Conference IEEE SouthWest Test WorkShop, 2005.
[6] F. L. Taber, “An Introduction to Area Array Probing”, in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 277-281, 1998.
[7] M. Beiley, J. Leung & S. S. Wong, “A Micro-machined Array Probe Card Fabrication Process,” IEEE Transactions on components, package and manufacturing technology, vol.18, no. 1, pp. 179-183, 1995.
[8] K. F. Zimmermann, “Si Probe-A New Technology for Wafer Probing,” in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 106-112, 1995.
[9] B. Pardee & B. Fulton, “Using MLO Packages to Build Vertical Probe Space Transformers,” in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 1-25, 2002.
[10] DSL Labs, Inc. 2007. Available: http://www.dsllab.net/products/vertical.html.
[11] Q. Qiao, “Development of a Wafer-Level Burn-In Test Socket for Fine-Pitch BGA Interconnect,” in Proc. of Electronic Components and Technology Conference, pp. 1147-1151, 2002.
[12] S. Chowdhury, “A MEMS socket system for high density SoC interconnection,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 657-660, 2002.
[13] D. Y. Shih, “New ball grid array module test sockets,” in Proc. of Electronic Components and Technology Conference, pp. 467-470, 1996.
[14] B. Chan & P. Singh, “BGA sockets-a dendritic solution,” in Proc. of Electronic Components and Technology Conference, pp. 460–466, 1996.
[15] H. Y. Chang, W. F. Pan, C. C. Wang, Y. C. Taso & J. S. Chiang, “Electrical Characterization of Micro Spring Probe Card for Wafer Level Testing,” In Proc. of ICEP (9th International Conference on Electronics Packaging), Kyoto, Japan, pp. 1-6, 2009.
[16] FormFactor, Inc. (2011) Available:http://www.formfactor.com/tech_prod/dram/ PH150XP_PH.html.
[17] R. Martens, “MicroForce™ Probing for Devices with Low with Low-k ILD Materials,” in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 1-22, 2003.
[18] M. Brandemuehl, “Introduction to FormFactor’s No-Clean Probe Card Technology,” in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 4-5, 1999.
[19] Cascade Microtech, Inc. (2011). Available:http://www.cmicro.com/products/ probe-cards/the-technology/pyramid-probe-card-technology
[20] K. Smith, “Membrane Cards With Microscrub Technology, ” In Proc. of IEEE SouthWest Test WorkShop, 1999.
[21] S. Maekawa, M. Takemoto, Y. Kashiba, Y. Deguchi, K. Miki & T. Nagata, “Highly reliable probe card for wafer testing,” IEEE Electronic Components and Technology Conference, pp. 1152-1156, 2000.
[22] M. J. Varnau, “Impact of wafer probe damage on flip chip yields and reliability,” in Proc. of IEEE/CPMT-IEMT, pp. 293–297, 1996.
[23] Hotchkiss, G., Ryan, G., Subido, W., Broz, J., Mitchell, S., Rincon, R., Rolda, R. & Guimbaolibot, L., “Effect of Probe Damage on Wire Bond Integrity,” IEEE Electronic Components and Technology Conference, 2001.
[24] Q. Tan, C. Beddingfield, & A. Mistry, “Reliability evaluation of probe-before- bump technology,” in Proc. IEEE/CPMT-IEMT, pp. 320-324, 1999.
[25] A. R. Comeau & N. Nadeau, “Modeling the bending of probes used in semiconductor industry,” IEEE Semicond. Manuf., vol. 4, no. 2, pp. 122-127, 1991.
[26] G. Hotchkiss, G. Ryan, W. Subido, J. Broz, S. Mitchell, R. Rincon, R. Rolda & L. Guimbaolibot, “Effect of probe damage on wire bond Integrity,” in Proc. of IEEE Electronic Components and Technology Conference, pp. 1175–1180, 2001.
[27] D. S. Liu & M. K. Shih, “An Experimental and Numerical Investigation into Multilayer Probe Card Layout Design,” in Proc. of IEEE/CPMTEPM, pp. 163–171, 2006.
[28] D. S. Liu & M. K. Shih, “Experimental method and FE simulation model for evaluation of wafer probing parameters,” Microelectronics Journal, vol. 37, no. 9, pp. 871-883, May, 2006.
[29] M. J. Varnau, “Impact of wafer probe damage on flip chip yields and reliability,” in Proc. of IEEE/CPMT-IEMT, pp. 293-297, 1996.
[30] M. Beiley, J. Leung & S. S. Wong, ”A Micro-machined Array Probe Card Fabrication Process,” in Proc. of IEEE Transactions on components, package and manufacturing technology, vol. 18, 1995.
[31] L. K. Cheah, Y. M. Tan, J. Wei & C. K. Wong, “Gold to gold thermosonic flip chip bonding,” in Proc. of International Conference on High-Density Interconnect and Systems Packaging, pp. 165-170, 2001.
[32] Y. C. Tsao, J. J. Tang & Y. L. Hsieh, "Analysis of Probing Effects on Solder Bump,” in Proc. of Electronics Packaging Technology Conference, pp. 303-306, 2004.
[33] P. Mai, K. Okubo, S. Kozaki & T. Sakata, “Vertical Contact Probe Card (VCPCTM),” in Proc. of the International Conference IEEE Southwest Test Workshop, pp. 106-112, 1997.
[34] D. T. Read & J. W. Dally, “Mechanical behavior of aluminum and copper thin films,” in Proc. ASME-IMECE, pp. 41-49, 1994.
[35] H. Y. Chang, W. F. Pan & S. M. Lin, “Investigation and Design of a Needle for Wafer Probing,” Precision Engineering, vol. 35, no. 2, pp. 294-301, April 2011.
[36] J. J. Broz & R. M. Rincon, “Probe contact resistance variations during elevated temperature wafer test,” In Proc. of IEEE Itc International Test Conference, pp. 396-405. 1999.
[37] Advanced Probing Systems, Inc. (2002). Available:http://www. advancedprobing.com/.
[38] V. Brizmer, Y. Kligerman & I. Etsion, “The effect of contact conditions and material properties on the elasticity terminus of a spherical contact,” Int J Solids Struct, vol. 43, no. 5, pp. 5736-5749, 2006.
[39] J. H. Lau , “Modeling analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on build up microvia prointed circuit board,” IEEE Transaction on Electronics Packaging Manufacturing, vol. 25, no. 1, pp. 51-58, 2002.
[40] B. A. Zahn, “Comprehensive solder fatigue and thermal characterization of a silicon based multi-chip module package utilizing finite element analysis methodologies,” in Proc. of 9th International ANSYS Conference, pp. 1-15, 2000.
[41] G Yu & N. Toshio, “Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages,” Microelectronics Reliability, vol. 44, no. 3, pp. 471-483, 2004.
[42] L. Kogut & I. Etsion, “Elastic-Plastic Contact Analysis of a Sphere and a Rigid Flat,” Journal of Applied Mechanics, vol. 69, no. 5, pp. 657-663, 2002.
[43] K. L. Johnson, Contact Mechanics, Cambridge, New York: Cambridge University Press, 1989.
[44] H. Y. Chang, W. F. Pan, M. K. Shih & Y. S. Lai, “Geometric Design for Ultra- Long Needle Probe Card for Digital Light Processing Wafer Testing,” Microelectronics Reliability, vol. 50, no. 4, pp. 556-563, 2010.
[45] H. Y. Chang, W. F. Pan, M. K. Shih, Y. S. Lai & Y. C. Tsao, “Ultra long needle geometry probe card development for wafer level test,” In Proc. of 3rd IMPACT (International Microsystems, Packaging, Assembly and Circuits Technology Conference) and 10th EMAP (International Conference on Electronics Materials and Packaging) Joint Conference, Taipei , pp. 128-131, 2008.
[46] H. Y. Chang, W. F. Pan, M. K. Shih & Y. S. Lai, “Experimental investigation and finite element analysis of bump wafer probing,” In Proc. of IMPACT (4th International Microsystems, Packaging, Assembly and Circuits Technology Conference), Taipei, pp. 514-517, 2009.
[47] W. R. Chang, I. Etsion & D. B. Bogy, “An Elastic-Plastic Model for the Contact of Rough Surfaces,” ASME Journal of Tribology, vol. 109, no. 2, pp. 257-263, 1987.
[48] W. R. Chang, I. Etsion & D. B. Bogy, “Adhesion Model for Metallic Rough Surfaces,” ASME Journal of Tribology, vol. 110, no. 1, pp. 50-56, 1988.
[49] W. R. Chang, I. Etsion & D. B. Bogy, “Static Friction Coefficient Model for Metallic Rough Surfaces,” ASME Journal of Tribology, vol. 110, no. 1, pp. 57-63, 1988.
[50] D. Tabor, The Hardness of Metals, Oxford, UK: Clarendo