在本論文中，我們針對MPEG-4可變長度編解碼器提出一個低成本的實現方式，以兩個較小的字碼表取代一個很龐大的字碼表，減少所需的記憶體儲存容量。與其它方法做比較，我們的設計要求較少的記憶體儲存容量。依據合成結果，所提出的可變長度編解碼器皆具有低成本的優點。此外，我們提出一個新穎的方法去合併MPEG-1/2/4裡的字碼表，可以更有效地減少儲存容量。與其它可變長度解碼器做比較，我們的設計可解碼不同視訊壓縮標準，而且要求最小的晶片面積。
然後，本論文亦針對H.264的適應性可變長度編碼器與適應性二進制算術編碼器提出有效的硬體架構。一般而言，適應性可變長度編碼器使用大量字碼表進行編碼，所以需要相當大的儲存容量與硬體成本，為了降低成本，我們對不同性質的字碼表分別提出合適的實現方式。與其它適應性可變長度編碼器做比較，我們的電路要求最少的邏輯閘數。在H.264中，適應性二進制算術編碼器提供很好的壓縮率，不過它的運算複雜度也較高，因此需要設計一個合適的硬體架構。此外，適應性二進制算術編碼器需要使用到之前的編碼資訊，所以快速且正確的獲得這些資訊是很重要的。在本論文中，我們提出一個新的方法對之前的編碼資訊做管理與儲存。依據合成結果，我們的設計不只要求較低的成本，而且編碼效率也比其它適應性二進制算術編碼器更佳。
所有的硬體架構之實現是使用Verilog硬體描述語言，然後電路合成則是利用SYNOPSYS的Design Vision以及TSMC/UMC的標準元件庫。依據合成結果，我們的設計在硬體成本與速度皆具極佳的競爭力。

We present a low cost implementation technique for MPEG-4 variable length coding (VLC) in this dissertation. Two smaller tables are adopted in place of a large codeword table. Compared with other VLC techniques for MPEG-4 application, our design needs the least memory space. Synthesis results show that our VLC encoder and decoder both have the advantage of low cost. Moreover, we propose a novel method to merge MPEG-1/2/4 VLC tables and reduce the required storage space. Compared with other variable length decoders, the proposed design can outperform them with less hardware cost.
In this dissertation, a context-based adaptive variable length coding (CAVLC) encoder and a context-based adaptive binary arithmetic coding (CABAC) encoder are both realized. We present an efficient technique for CAVLC encoder. Synthesis results demonstrate that the gate count of our design is less than previous CAVLC chips. Besides, a new design of context modeler for CABAC encoder is proposed. The well-organized location-index assignment and the copy-and-paste technique are employed to locate, store and retrieve the needed syntax elements both easily and efficiently with less storage space. The synthesis results show that the proposed CABAC encoder outperforms others with less hardware cost.
The VLSI architectures of the proposed design were implemented by using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the designs with TSMC or UMC cell library. Synthesis results demonstrate that our designs have the advantages of low cost and high performance.

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