本論文研製應用於 Ka 頻段射頻收發前端之三項核心電路，包括低雜訊放大器、多爾蒂功率放大器及單刀雙擲開關。三項電路均採用穩懋 0.12 μm 氮化鎵 HEMT 製程設計，其中低雜訊放大器與多爾蒂功率放大器已完成晶片製作與量測，單刀雙擲開關則以佈局後電路及電磁共模擬進行驗證。
低雜訊放大器採用具電感性源極退化之共源極三級架構，並以傳輸線與電容構成兼具阻抗匹配與帶外抑制之帶通型匹配網路。量測結果顯示，其峰值增益約為 34 dB；於 26–28 GHz 內，增益為 29–34 dB，輸出回波損耗大於 10 dB。雜訊指數於 26.5–29 GHz 內低於 3 dB，最低約為 2.7 dB。輸出 1-dB 壓縮點為 18 dBm，直流功率消耗為 0.54 W，晶片面積為 2.9 × 0.9 mm²。輸入端係以雜訊匹配優先於功率匹配，故輸入回波損耗僅約 5 dB。
多爾蒂功率放大器採用單一驅動級架構，以改善功率回退條件下之效率。量測之小訊號 3-dB 頻寬為 26.5–29.2 GHz，峰值小訊號增益約為 19.5 dB，輸入與輸出回波損耗皆大於 8 dB。於 28.5 GHz、輸入功率 17 dBm（量測系統可提供之最大驅動功率）條件下，輸出功率達 31.2 dBm，此時電路尚未進入飽和；峰值功率附加效率為 22.7%，於 6-dB 功率回退點（25.2 dBm）仍維持 13.8% 之功率附加效率。上述結果顯示本設計具備瓦級輸出能力，惟峰值與回退效率仍低於原訂規格，後續可由主、輔放大器之導通條件與輸出匹配網路進一步改善。
單刀雙擲開關採用對稱匹配型架構，並將電晶體之導通電阻、關斷電容及高頻寄生電感一併納入元件模型，以降低隔離支路對導通支路之負載效應。佈局後模擬結果顯示，於 26–30 GHz 內，插入損耗為 2.3–2.4 dB、回波損耗大於 20 dB、隔離度大於 27 dB；於 28 GHz 之輸入 1-dB 壓縮點為 30.5 dBm，晶片面積為 2.9 × 0.9 mm²。
整體而言，本論文所完成之量測與模擬結果，可作為後續單晶片全氮化鎵 Ka 頻段射頻前端整合之設計基礎。

This thesis presents the design of three core circuits for a Ka-band RF transceiver front-end: a low-noise amplifier (LNA), a Doherty power amplifier (DPA), and a single-pole double-throw (SPDT) switch. All three circuits are designed in the WIN Semiconductors 0.12-μm GaN HEMT process. The LNA and the DPA were fabricated and experimentally characterized, whereas the SPDT switch was evaluated through post-layout electromagnetic and circuit co-simulation.
The LNA employs a three-stage inductively degenerated common-source topology, in which transmission lines and capacitors form a bandpass matching network that provides both impedance matching and out-of-band rejection. The measured peak gain is approximately 34 dB, and the gain ranges from 29 to 34 dB over 26–28 GHz, with an output return loss greater than 10 dB. The measured noise figure remains below 3 dB from 26.5 to 29 GHz, with a minimum of 2.7 dB. The output 1-dB compression point is 18 dBm, the dc power consumption is 0.54 W, and the chip occupies 2.9 × 0.9 mm². The input network is matched for minimum noise rather than for maximum power transfer, which accounts for the input return loss of about 5 dB.
The DPA adopts a single driver stage to improve efficiency under power back-off. The measured small-signal 3-dB bandwidth is 26.5–29.2 GHz, the peak small-signal gain is approximately 19.5 dB, and both the input and output return losses are greater than 8 dB. At 28.5 GHz and an input drive of 17 dBm, which is the maximum drive available in the measurement setup, the output power reaches 31.2 dBm; the amplifier has not yet been driven into saturation at this point. The peak power-added efficiency (PAE) is 22.7%, and the PAE at the 6-dB back-off point (25.2 dBm) is 13.8%. These results confirm watt-level output capability, although both the peak and the back-off PAE remain below the target specifications, indicating that the turn-on condition of the auxiliary amplifier and the output matching network can be further improved.
The SPDT switch uses a symmetric matched-type topology. The on-resistance, the off-capacitance, and the high-frequency parasitic inductance of the transistor are all included in the device model in order to mitigate the loading effect of the isolated branch on the through branch. Post-layout simulation shows an insertion loss of 2.3–2.4 dB, a return loss greater than 20 dB, and an isolation greater than 27 dB over 26–30 GHz, together with an input 1-dB compression point of 30.5 dBm at 28 GHz, within a chip area of 2.9 × 0.9 mm².
Taken together, the measured and simulated results reported in this thesis provide a design baseline for the subsequent monolithic integration of an all-GaN Ka-band RF front-end.

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