隨著積體電路（IC）製程的日益複雜化與市場需求的提升，提高良率已成為半導體行業的重要議題。透過識別潛在的IC缺陷類型並分配適合的工程師來解決這些問題，可以減少損失並加快產品上市的時間。現有的方法往往忽略了處理任務所需的時間和各個工程師的技能。基於此情況，我們提出了一種創新的方法，利用圖結構對積體電路模組中的缺陷類型進行建模，並通過對比匹配方法識別最適合或最有經驗的工程師。這一方法不僅優化了IC測試中的任務分配，還通過確保任務由最能勝任的工程師來完成，平衡工作負載，並促進工程師在處理不同缺陷類型方面的經驗多樣性。通過對真實數據集的實驗，我們證明了此方法在將適當的工程師分配給各種IC模組缺陷類型的任務中，比基準方法取得了更高的成功率。此外，該方法還有效平衡了每位工程師的工作負荷，並同時考慮了他們處理缺陷類型的多樣性。

As integrated circuit (IC) processes become increasingly complex and market demands rise, enhancing yield has become a critical factor for the semiconductor industry. Identifying potential IC defect types and assigning the corresponding engineers to address them can mitigate losses and expedite time-to-market. Existing approaches often ignore the time required to handle tasks and the competencies of individual engineers. Motivated by this, we propose an innovative method that models the probabilities of defect types in IC modules through a graph structure and utilizes a contrasting matching method to identify the most suitable or proficient engineers. This approach not only optimizes task assignment in IC testing but also improves human resource management by ensuring tasks are handled by the most capable engineers, balancing workloads, and promoting diverse experience in addressing different defect types. Through experiments on a real-world dataset, we demonstrate that this method achieves the highest number of successful task assignments to appropriate engineers for various defect types in IC modules compared to baseline methods. Additionally, it effectively balances each engineer's workload and considers the variety of defect types they handle.

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