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研究生：	謝怡伶 Hsieh, Yi-Ling
論文名稱：	動態適應性解交錯演算法之設計與電路實作 The design and VLSI implementation of a motion-adaptive de-interlacing algorithm
指導教授：	陳培殷 Chen, Pei-Yin
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	39
中文關鍵詞：	電路實作、解交錯演算法
外文關鍵詞：	de-interlacing algorithm, VLSI
相關次數：	點閱：58 下載：0
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本論文提出一個低複雜度的動態適應性解交錯演算法。所提出的方法利用三幅連續的場(field)將像素狀態區分為移動與靜止。對於判斷為移動狀態的像素，即沿著移動方向做插補(interpolation)；對於判斷為靜止的像素，則利用時間與空間的關係求出像素值。在電路實作上，以硬體描述語言(Verilog HDL)寫成，並以TSMC .18 μm 製程合成電路，且將電路管線化(pipelined)以達到效率的要求。合成後的電路工作頻率可達200MHz，邏輯閘數目估計約為18,581個。

In this thesis, a low-complexity motion-adaptive de-interlacing algorithm is presented. This algorithm uses three consecutive interlaced video fields for motion detection, which classifies pixels as moving or stationary. For a moving pixel, bilinear interpolation is performed along the direction of motion. And for a stationary pixel, a spatial-temporal interpolation scheme that exploits edge detection is used. The VLSI architecture is designed and implemented with TSMC 0.18 μm technology, and we adopt the pipelined scheduling approach to achieve the goal of efficiency. The operating speed of our design is 200 MHz, and the number of gates is approximately 18,581.

中文摘要 ................................................I
Abstract ...............................................II
Acknowledgements ......................................III
Table of Contents ......................................IV
List of Figures .......................................VII
List of Tables .........................................IX
Chapter 1  Introduction ................................1
Chapter 2  De-interlacing Techniques ...................4
  2.1.  Problem Description ............................4
  2.2.  Spatial Methods ................................5
    2.2.1.  Line Doubling ..............................6
    2.2.2.  Line Averaging .............................6
    2.2.3.  Edge-based Line Average (ELA) ..............6
  2.3.  Spatial-temporal Methods .......................7
    2.3.1.  Field Insertion ............................8
    2.3.2.  Field Average ..............................8
    2.3.3.  Spatio-temporal Edge-based Median Filtering (ST-ELA) ...8
  2.4.  Motion-adaptive Methods ........................9
  2.5.  Motion-compensated Methods ....................10
Chapter 3  Proposed Method ............................11
  3.1.  Motion Detector ...............................12
  3.2.  Motion-based Interpolator .....................13
  3.3.  Spatial-temporal Interpolator .................14
Chapter 4  VLSI Implementation ........................17
  4.1.  System Architecture ...........................17
  4.2.  Register Bank .................................18
  4.3.  Motion Detector ...............................19
  4.4.  Spatial-temporal Directional Difference Calculator ........20
  4.5.  Interpolators .................................21
  4.6.  Minimum of Six Numbers ........................22
  4.7.  Minimum of Nine Numbers .......................23
Chapter 5  Experimental Results .......................25
  5.1.  Peak-signal-to-noise ratio (PSNR) .............25
  5.2.  Execution Time ................................29
  5.3.  Visual Quality ................................30
  5.4.  Hardware Implementation Result ................34
Chapter 6  Conclusion and Future Work …...............35
  6.1.  Conclusion ....................................35
  6.2.  Future Work ...................................35
References ............................................37
                                    

[1] T. Doyle, “Interlaced to sequential conversion for EDTV applications,” Proc. 2nd Int. Workshop on Signal Processing of HDTV, pp. 421-430, Feb. 1988.

[2] H.-S. Oh, Y. Kim, Y.-Y. Jung, A. W. Morales, and S.-J. Ko, “Spatio-temporal edge-based median filtering for deinterlacing,” IEEE International Conference on Consumer Electronics, pp. 52-53, 2000.

[3] S.-F. Lin, Y.-L. Chang, and L.-G. Chen, “Motion adaptive interpolation with horizontal motion detection for deinterlacing,” IEEE Transactions on Consumer Electronics, Vol. 49, No. 4, pp. 1256-1265, Nov. 2003.

[4] M.-J. Chen, C.-H. Huang, and C.-T. Hsu, “Efficient de-interlacing technique by inter-field information,” IEEE Transactions on Consumer Electronics, Vol. 50, No. 4, pp. 1202-1208, Nov. 2004.

[5] G.-L. Li and M.-J. Chen, “High performance de-interlacing algorithm for digital television displays,” Journal of display technology, Vol. 2, No. 1, pp. 85-90, Mar. 2006.

[6] C.-C. Lin, M.-H. Sheu, H.-K. Chiang, C.-J. Wei, and C. Liaw, “A high-performance architecture of motion adaptive de-interlacing with reliable interfield information,” IEICE Trans. Fundamentals, Vol. E90-A, No. 11, pp. 2575-2583, Nov. 2007.

[7] K. Sugiyama and H. Nakamura, “A method of de-interlacing with motion compensated interpolation,” IEEE Transactions on Consumer Electronics, Vol. 45, No. 3, pp. 611-616, Aug. 1999.

[8] Y.-Y. Jung, B.-T. Choi, Y.-J. Park, and S.-J. Ko, “An effective de-interlacing technique using motion compensated interpolation,” IEEE Transactions on Consumer Electronics, Vol. 46, No. 3, pp. 460-466, Aug. 2000.

[9] Q. Huang, W. Gao, D. Zhao, and H. Sun, “An efficient and robust adaptive deinterlacing technique,” IEEE Transactions on Consumer Electronics, Vol. 52, No. 3, pp. 888-895, Aug. 2006.

[10] H. M. Mohammadi, P. Langlois, and Y. Savaria, “A five-field motion compensated deinterlacing meghod based on vertical motion,” IEEE Transactions on Consumer Electronics, Vol. 53, No. 3, pp. 1117-1124, Aug. 2007.

[11] Y.-C. Fan, H.-S. Lin, A. Chiang, and C.-C. Kuo, “Motion compensated deinterlacing with efficient artifact detection for digital television displays,” Journal of display technology, Vol. 4, No. 2, pp. 218-228, Jun. 2008

[12] D.-H. Lee, “A new edge-based intra-field interpolation method for deinterlacing using locally adaptive-thresholded binary image,” IEEE Transactions on Consumer Electronics, Vol. 54, No. 1, pp. 110-115, Feb. 2008.
[13] C. Wang, H. Han, and S. Peng, “A spatial deinterlacing algorithm based on edge orientation optimized in local area,” Congress on Image and signal Processing, pp. 87-91, 2008.

[14] C.-C. Lin, C.-J. Wei, M.-H. Sheu, and H.-K. Chiang, “The VLSI design of motion adaptive de-interlacing with horizontal and vertical motions detection,” IEEE APCCAS 2006, pp. 1589 - 1592, Dec. 2006.

[15] H. Sun, N. Zheng, C. Ge, D. Wang, and P. Ren, “An efficient motion adaptive de-interlacing and its VLSI architecture design,” ISVLSI, pp. 455 - 458, Apr. 2008.

校內：2089-06-24公開
校外：2089-06-24公開電子論文尚未授權公開，紙本請查館藏目錄

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