在本篇論文中，吾人首先運用所建構之互補式多脈波量測技術(CMPT)調查高介電係數介電層-金屬閘極之金氧半場效應電晶體在正偏壓溫度不穩定應力施加下介電層載子捕陷(trapping)之特性。互補式多脈波量測技術可有效降低可靠度量測過程中高介電係數介電層所產生之去捕陷效應，進而更加準確評估高介電係數元件之可靠度。透過互補式多脈波量測技術吾人觀察到較大之臨限電壓偏移並發現高介電係數介電層/矽基板間之二氧化矽介面層厚度影響量測結果甚巨。吾人並提出高介電係數介電層-金屬閘極之金氧半場效應電晶體之正偏壓溫度不穩定可靠度劣化機制之模型。為了能夠進一步了解高介電係數材料中電荷捕陷之機制，吾人透過改變高介電係數介電層厚度以及變頻電荷汲引技術(charge pumping)描繪出高介電係數薄膜中缺陷之分布。
其次，吾人詳細研究高介電係數介電層-雙金屬閘極之金氧半場效應電晶體之溫度偏壓不穩定之特性。並研究包括氮離子以及鋯(Zr)離子摻雜至高介電係數介電層對元件特性以及偏壓不穩定性之影響。吾人發現鋯離子摻雜可有效降低薄膜中缺陷數量且不會劣化介面品質。因此，鋯離子摻雜可提高元件之載子遷移率約25%，並使元件擁有較高抵抗正偏壓溫度不穩定性之能力。另一方面，相較於在二氧化矽界面層中摻雜氮離子，在高介電係數薄膜中摻雜氮離子能更有效降低反轉氧化層厚度而不造成過多之載子遷移率劣化。在高介電係數薄膜中摻雜氮離子亦能透過降低缺陷數量提供較佳之正偏壓溫度不穩定特性。然而，在高介電係數薄膜中摻雜之氮離子會降低介電層與金屬間之能位障高度並產生較高之漏電流。吾人亦運用定電場以及定電壓偏壓應力之施加來研究氮化矽覆蓋層所產生之應力以及元件通道長度對於高介電係數金氧半場效應電晶體之正偏壓溫度以及負偏壓溫度不穩定性之影響。當元件通道長度大於0.1 m時，氮化矽所產生之應力並未對正負偏壓溫度不穩定性產生影響，然而隨著元件尺寸微縮，氮化矽所產生之應力依然未影響正偏壓不穩定性。另一方面，負偏壓溫度不穩定性受應力之影響而產生劣化現象。
再則，吾人亦深入探討在高介電係數元件之本體缺陷(bulk traps)增強閘極引發汲極漏電流(GIDL)發生機制。吾人利用摻雜不同鋯濃度之鋯氧化鉿介電層、不同厚度之氧化鉿介電層以及不同電應力施加來研究在高介電係數元件中電荷捕陷與本體缺陷增強閘極引發汲極漏電流之關係。實驗結果指出較薄介電層以及鋯摻雜較濃之元件可有效降低閘極引發汲極漏電流。藉由不同電應力施加實驗建立高介電係數元件中本體缺陷與閘極引發汲極漏電流之模型。此外並進一步研究在二氧化鉿以及氮氧化矽介電層元件中，淺溝槽隔離(STI)所產生之應力對於閘極引發汲極漏電流之影響。在二氧化鉿元件中，不管在高電壓或低電壓區域淺溝槽隔離所產生之應力全面性並大幅度的增加閘極引發汲極漏電流。另一方面，應力僅稍微增加氮氧化矽元件之閘極引發汲極漏電流。根據實驗結果，吾人亦提出較佳之電路佈局(Layout)方式以降低淺溝槽隔離應力對於閘極引發汲極漏電流之影響。
最後，吾人針對低溫多晶矽薄膜電晶體之動態負偏壓溫度不穩定性進行研究。實驗結果顯示，其動態負偏壓溫度不穩定性展現和傳統金氧半場效應電晶體不同之頻率響應，負偏壓溫度不穩定性所產生之劣化隨著應力頻率增加而降低。吾人認為晶粒邊界與矽/二氧化矽介面不同之載子反轉時間常數是造成低溫多晶矽薄膜電晶體之動態負偏壓溫度不穩定性頻率響應之主要原因。

In this thesis, the trapping characteristics of positive bias temperature instability (PBTI) on a high-k/metal gate n-type metal oxide semiconductor field effect transistor (nMOSFET) have been firstly investigated with a complementary multi-pulse technique (CMPT) in detail. With the CMPT technique, we find that the threshold voltage shifts after PBTI are higher than that with the conventional direct current method, and the thickness of the SiO2 interfacial layer has a significant effect on the measured results. The observation of these new results is attributed to the CMPT technique has the unique feature of effectively reducing the detrapping effect induced by the large bulk traps existed in high-k dielectrics. Besides, based on the results, the mechanism of PBTI in metal gate/high-k nMOSFETs is modeled. Furthermore, with the terrace high-k method and the frequency-dependent charge pumping technique, the profile of bulk traps in the Hf-based dielectric is sketched to further understand the mechanism of trapping in high-k dielectrics.
Secondly, the bias temperature instability of dual metal gate CMOSFETs with Hf-based dielectrics including HfO2 and HfSiON has been extremely investigated. The influences of high-k gate stacks engineering including zirconium and nitrogen incorporation on performance and BTI of high-k/metal gate MOSFET are studied. We find that the density of bulk traps is reduced with increasing Zr content with a comparable Dit value. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ~25% mobility enhancement compared with that of HfO2 can be observed. The improvement in PBTI is also demonstrated with DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. On the other hand, experimental results revealed the high-k dielectric nitrogen annealing is a better solution for the trade-off between mobility and inversion oxide thickness (TOX, INV) than IL nitrogen annealing. In addition, the positive bias temperature instability (PBTI) characteristic is improved through reducing the quantity of bulk traps. However, the high-k dielectric nitrogen annealing also lowers the barrier of dielectric and thus results in an abnormally higher leakage current. Furthermore, the strain effect from a tensile SiN capping layer, as well as the channel length dependence, on both NBTI and PBTI of the high-k gate stack devices are studied. For channel length larger than 0.1 µm, both PBTI and NBTI are not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 µm, the degradation after PBTI stress is still not influenced by the strain, however, the NBTI degradation is enhanced significantly. In addition, the dependence of BTI on channel length is extensively investigated under constant voltage and field stress.
Thirdly, a comprehensive study on bulk trap enhanced gate induced drain leakage currents (BTE-GIDL) in high-k MOSFETs is reported. The dependence of GIDL for various parameters including the effect of Zr concentration in HfZrOX, high-k film thickness, and electrical stress is investigated. The incorporation of Zr into HfO2 reduces GIDL. GIDL is also found to reduce with thinner high-k film. In addition, a significant correlation between GIDL and bulk trap density in high-k film is established. Possible mechanisms are provided to explain the role of bulk trapping in BTE-GIDL. Furthermore, the effects of shallow trench isolation (STI) induce mechanical strain on GIDL current in Hf-based and SiON nMOSFETs are investigated in detail. The STI-induced mechanical strain enhances the GIDL current including the trap-assisted tunneling (TAT) component at low voltage and the band-to-band tunneling (BBT) component at high voltage. The compressive strain induced band narrowing and the increase of intrinsic carrier concentration are attributed to the root cause of GIDL increment, respectively. However, different strain sensitivities of GIDL are observed on HfO2 and SiON nMOSFETs. The higher density of interface states induced by mechanical strain is responsible for the higher strain sensitivity observed on HfO2 devices. The symmetric layout shows higher ability to suppress the STI-enhanced GIDL current with same active area length.
Finally, the dynamic NBTI on low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) is investigated in detail. Experimental results reveal the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different to the frequency-independent of conventional CMOSFET. The difference of transit time between grain boundary and Si/SiO2 interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency.

References:
[1.1] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on High-k Dielectrics Reliability Issues”, IEEE Trans. Device and Materials Reliability,Vol. 5, pp. (2005).
[1.2] E. P. Gusev, “The physics and chemistry of SiO and the Si-SiO interface”, Electrochem. Soc., pp. 477-485, (2000).
[1.3] H. Iwai, S.Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 625-628, (2002).
[1.4] T. Watanabe, M. Takayanagi, K. Kojima, K. Ishimaru, H. Ishiuchi, K. Sekine, H. Yamasaki,and K. Eguchi, “Impact of Hf concentration on performance and reliability for HfSiON-CMOSFET”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 507-510, (2004).
[1.5] H. C.-H. Wang, Shang-Jr Chen, Ming-Fang Wang, Pang-Yen Tsai, Ching-Wei Tsai, Ta-Wei Wang, S. M. Ting, Tuo-Hung Hou, Peng-Soon Lim, Huan-Just Lin, Ying Jin, Hun-Jan Tao, Shih-Chang Chen, C. H. Diaz, Mong-Song Liang, and Chenming Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 161-164, (2004).
[1.6] H.C.-H. Wang, Ching-Wei Tsai, Shang-Jr Chen, Chien-Tai Chan, Huan-Just Lin, Ying Jin, Hun-Jan Tao, Shih-Chang Chen, C. H. Diaz, Tongchern Ong, A. S. Oates, Mong-Song Liang, and Min-Hwa Chi, “Reliability of HfSiON as gate dielectric for advanced CMOS technology”, VLSI Symp. Tech. Dig., pp. 170-171, (2005).
[1.7] J. C. Liao, Y. K. Fang, Y. T. Hou, W. H. Wu, C. L. Hung, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, “Observations in trapping characteristics of positive bias temperature instability on high-k/metal gate n-type metal oxide semiconductor field effect transistor with the complementary multi-pulse technique”, Thin Solid Films, 516, pp. 4222-4225, (2008).
[1.8] J. C. Liao, Y. K. Fang, Y. T. Hou, W. H. Tseng, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, “Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs”, IEEE Electron Device Lett., Vol. 29, pp. 509-511, (2008).
[1.9] J. C. Liao, Y. K. Fang, C. H. Kao, and C. Y. Cheng, “Dynamic Negative Bias Temperature Instability (NBTI) of Low-Temperature Polycrystalline Silicon (LTPS) Thin-Film Transistors”, IEEE Electron Device Lett., Vol. 29, pp. 477-479, (2008).
[2.1] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors”, IEEE Trans. Electron Devices, Vol. 37, pp. 654-660, (1990).
[2.2] F. H. Hooge, and L. K. J. Vandamme, “Lattice scattering causes 1/f noise”, Phys. Lett., Vol. 66A, pp. 315-321, (1978).
[2.3] R. E. Paulsen and M. H. White, “Theory and Application of Charge Pumping for the Characterization of Si-SiO2 Interface and Near-Interface Oxide Traps” IEEE Trans. Electron Devices, Vol. 41, pp. 1213-1216, (1994).
[2.4] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k dielectrics reliability issues”, IEEE Trans. Device and Materials Reliability,Vol. 5, pp. 5, (2005).
[2.5] D. Heh, R. Choi, C. D. Young, B. H. Lee, and Gennadi Bersuker, “A Novel Bias Temperature Instability Characterization Methodology for High-k nMOSFETs”, IEEE Electron Device Lett., Vol. 27, pp. 849-851, (2006).
[2.6] T. H. Wang, C. T. Chan, C. J. Tang, C. W. Tsai, C. H. Wang, M. H. Chi, and D. Tang, “A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient”, IEEE Trans. Electron Device, Vol. 53, pp. 1073-1079, (2006).
[2.7] J. Mitard, X. Garros, L.P. Nguyen, C. Leroux, G. Ghibaudo, F. Martin, and G. Reimbold, “Large-Scale Time Characterization and Analysis of PBTI In HFO2/Metal Gate Stacks”, IEEE International Reliability Physics Symp. pp. 174-178, (2006).
[2.8] K. A. Jenkins and J. Y. -C. Sun, “Measurement of I-V curves of Silicon-on-Insulator (SOI) MOSFETs without self-heating”, IEEE Electron Device Lett., Vol. 16, pp. 145-147, (1995).
[2.9] D. V. Singh, P. Solomon, E. P. Gusev, G. Singo, and Z. Ren, “Ultra-fast measurements of the inversion charge in MOSFETs an impact on measured mobility in high-k MOSFETs ”, Tech. Dig. IEEE International Electron Devices Meeting pp. 863-866, (2004).
[2.10] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groesenken, H. E. Maes, and U. Schwalke, “Characterization of the Vt-instability in SiO2/HfO2 gate dielectrics”, IEEE International Reliability Physics Symp. pp. 41-45, (2003).
[2.11] C. Shen, M. -F. Li, X. P. Wang, Y. -C. Yeo, and D. L. Kwong, “A fast measurement technique of MOSFET Id-Vg characteristics”, IEEE Electron Device Lett., Vol. 27, pp. 55-57, (2006).
[2.12] C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, “Characterization and modeling of hysteresis phenomena in high K dielectrics”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 737-740, (2004).
[2.13] Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen and M. S. Liang, “High performance Tantalum Carbide metal gate stacks for nMOSFET application”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 31-34, (2005).
[2.14] G. Ribe, M. Miiller, S. Bruyere, D. Roy, M. Denais, V. Huard, T. Skotnicki, and G. Ghibaudo, “Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques”, Proceeding IEEE European Solid-State Device Research Conference. pp. 89-92, (2004).
[2.15] M. Denais, C. Parthasarathy, G. Ribes, , Y. Rey-Tauriac, N. Revil, A. Bravaix, V. Huard, and F. Perrier, “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 109-112, (2004).
[2.16] J. Kang, E. C. Lee, K. J. Chang, and Y. G. Jin, “H-related defect complexes in HfO2: A model for positive fixed charge defects”, Appl. Phys. Lett., Vol. 84, 3894, (2004).
[2.17] G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, S. Nadkarni, R. Choi, and B. H. Lee, “Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors”, IEEE International Reliability Physics Symp. pp. 179-183, (2006).
[2.18] H. C. Wen, R. Choi, G. A. Brown, T. Bscke, K. Matthews, H. R. Harris, K. Choi, H. N. Alshareef, H. Luan, G. Bersuker, P. Majhi, D. L. Kwong, and B. H. Lee, “Comparison of effective work function extraction methods using capacitance and current measurement techniques”, IEEE Electron Device Lett., Vol. 27, pp. 598-601, (2006).
[2.19] H. -H Tseng, C. C.Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramon, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hegde, R. Noble, M. Jahanbani, C. El Chemali, B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2 stack”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 821-824, (2004).
[2.20] J. K Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H. -H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W. J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. Jr. White, P. J. Tobin, “Challenges for the integration of metal gate electrodes”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 287-190, (2004).
[2.21] F. Y. Yen, C. L. Hung, Y. T. Hou, P. F. Hsu, V. S. Chang, P. S. Lim, L. G. Yao, J. C. Jiang, H. J. Lin, C. C. Chen, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen, and M. S. Liang, “Effective work function engineering of TaxCy metal gate on Hf-based dielectrics”, IEEE Electron Device Lett. Vol. 28, pp. 201-203, (2007).
[2.22] R. S. Muller and T. I. Kamins, “Device Electronics for Integrated Circuits”, 3rd Eds. John Wiley & Sons Inc.
[2.23] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L.Dip, L. Hebert, R. Garcia, R. Hegde, J. Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak,; L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, and B. Nguyen, P. Tobin, “80-nm poly-Si gate CMOS with HfO2 gate dielectric,” Tech. Dig. IEEE International Electron Devices Meeting, pp. 30.1.1-30.1.4, (2001).
[2.24] G. D. Wilk, M. L. Green, M. -Y. Ho, B. W. Busch, T. W. Sorsch, F. P. Klemens, B. Brijs, R. B. van Dover, A. Kornblit, T. Gustafsson, E. Garfunkel, S. Hillenius, D. Monroe, P. Kalavade, and J. M. Hergenrother, “Improved film growth and flatband voltage control of ALD HfO2 and Hf-Al-O with n+ poly-Si gates using chemical oxides and optimized post-annealing”, VLSI Symp. Tech. Dig., pp. 88-89 (2002).
[2.25] R. Degraeve, F. Crupi, D. H. Kwak, and G. Groeseneken, “On the defect generation and low voltage extrapolation of QBD in SiO2/HfO2 stacks”, VLSI Symp. Tech. Dig., pp. 140-141, (2004).
[2.26] R. Degraeve, A. Kerber, P. Roussel, E. Cartier, T. Kauerauf, L. Pantisano, and G. Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 935-938, (2003).
[2.27] F. Crupi, R. Degraeve, A. Kerber, D. H. Kwak, and G. Groeseneken, “Correlation between stress-induced leakage current (SILC) and the HfO2 bulk trap density in a SiO2/HfO2 stack,” IEEE International Reliability Physics Symp., pp. 181-187, (2004).
[2.28] R. Degraeve, T. Kauerauf, M. Cho, M. Zahid, L.-A. Ragnarsson, D. P. Brunco, B. Kaczer, P. Roussel, S. De Gendt, and G. Groeseneken, “Degradation and breakdown of 0.9 nm EOT SiO2/ALD HfO2/metal gate stacks under positive constant voltage stress,” Tech. Dig. IEEE International Electron Devices Meeting, pp. 408-411, (2005).
[2.29] D. Heh, C. D. Young, G. A. Brown, P. Y. Hung, A. Diebold, and G. Bersuker, “Spatial distribution of trapping centers in HfO2/SiO2 gate stacks,” Appl. Phys. Lett., Vol. 88, pp. 152907, (2006).
[3.1] G. D. Wilk, W. M. Wallace and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations”, J. Appl. Phys., Vol. 89, 5243 (2001).
[3.2] H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS”, Tech. Dig. IEEE International Electron Devices Meeting pp. 625-628, (2002).
[3.3] P. F. Hsu, Y. T. Hou, F. Y. Yen, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, J. M. Chiou, K. M. Yin, J. J. Lee, R. L. Hwang, Y. Jin, S. M. Chang, H. J. Tao, S. C. Chen, M. S. Liang, and T. P. Ma, “Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application”, VLSI Symp. Tech. Dig., pp.14-15 (2006).
[3.4] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k dielectrics reliability issues”, IEEE Trans. Device and Materials Reliability,Vol. 5, pp. 5, (2005).
[3.5] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks” IEEE Trans. Device and Materials Reliability, Vol. 5, pp.45-64 (2005).
[3.6] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, J. Appl. Phys., 94, 1 (2003).
[3.7] T. P. Ma, M. Bu, X. W. Wang, L. Y. Song, W. He, M. Wang, H. H. Tseng, and P. J. Tobin, “Special reliability features for Hf-based high-k/gate dielectrics”, IEEE Trans. Device and Materials Reliability, Vol. 5, pp. 36-44, (2005).
[3.8] S. Kalpat, H. H. Tseng, M. Ramon, M. Moosa, D. Tekleab, P. J. Tobin, D. C. Gilmer, R. I. Hegde, C. Capasso, C. Tracy, and B. E. White, Jr., “BTI characteristics and mechanisms of metal gated HfO2 films with enhanced interface/bulk process treatments”, IEEE Trans. Device and Materials Reliability, Vol. 5, pp. 26-36 (2005).
[3.9] N. Sa, J. F. Kang, H. Yang, X. Y. Liu, Y. D. He, R. Q. Han, C. Ren, H. Y. Yu, D. S. H. Chan, and D. L. Kwong, “Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps”, IEEE Electron Device Lett., Vol. 26, pp. 610-612, (2005).
[3.10] R. I. Hegde, D. H. Triyoso, P. J. Tobin, S. Kalpat, M. E. Ramon, H.-H. Tseng, J. K. Schaeffer, E. Luckowski, W. J. Taylor, C. C. Capasso, D. C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R. S. Rai, L. Fonseca, M. Stoker, C. Tracy, B. W. Chan, Y. H. Chiu, and B. E. White, Jr., “Microstructure modified HfO2 using Zr addition with TaxCy gate for improved device performance and reliability”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 35-38, (2005).
[3.11] Y. T. Hou, J. C. Liao, P. F. Hsu, C. L. Hung, K. C. Lin, K. T. Huang, T. L. Lee, Y. K. Fang, and M. S. Liang, “BTI and Electron Trapping in Hf-based Dielectrics with Dual Metal Gates”, IEEE International Reliability Physics Symp. pp. 624-625, (2007).
[3.12] C. Choi, C. S. Kang, C. Y. Kang, R. Choi, H. J. Cho, Y. H. Kim, S. J. Rhee, M. Akbar, and Jack C. Lee, “The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature Instability”, VLSI Symp. Tech. Dig., pp.214-215, (2004).
[3.13] M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi, and A. Nishiyama, “Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 849-852, (2002).
[3.14] M. S. Akbar, H. -J. Cho, R. Choi, C. S. Kang, C. Y. Kang, C. H. Choi, S. J. Rhee, Y. H. Kim, and J. C. Lee, “Optimized NH3 annealing Process for high-quality HfSiON gate oxide”, IEEE Electron Device Lett., Vol. 25, pp. 465-467, (2004).
[3.15] M. A. Quevedo-Lopeza, S. A. Krishnan and P. D. Kirschb, G. Pant, B. E. Gnade, and R. M. Wallace, “Ultrascaled hafnium silicon oxynitride gate dielectrics with excellent carrier mobility and reliability”, Appl. Phys. Lett., vol. 87, 262902, (2005).
[3.16] H. S. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P. O. Hansson, M. Kim, H. S. Kim, N. I. Lee, “Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 692-695, (2005).
[3.17] K. Ichinose, T. Saito, Y. Yanagida, Y. Nonaka, K. Torii, H. Sato, N. Saito, S. Wada, K. Mori and S. Mitani, “A high performance 0.12 μm CMOS with manufacturable 0.18 μm technology”, VLSI Symp. Tech. Dig., pp.103-104, (2001).
[3.18] J. R. Shih, J. J. Wang, Ken Wu, Yeng Peng and J. Yue, “The study of compressive and tensile stress on MOSFET's I-V, C-V characteristics and it's impacts on hot carrier injection and negative bias temperature instability”, IEEE International Reliability Physics Symp., pp. 612-613, (2003).
[3.19] M. Houssa, M. Aoulaiche, S. V. Elshocht, S. D. Gendt, G. Groeseneken, and M. M. Heyns, “Negative bias temperature instabilities in HfSiON/TaN-based pMOSFETs”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 121-124, (2004).
[3.20] C. H. Choi, C. S. Kang, C. Y. Kang, S. J. Rhee, M. S. Akbar, S. A. Krishnan, M. H. Zhang, J. C. Lee, “Positive bias temperature instability effects of Hf-based nMOSFETs with various nitrogen and silicon profiles”, IEEE Electron Device Lett., Vol. 26, pp. 32-34, (2005).
[3.21] Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen, and M. S. Liang, “High performance tantalum carbide metal gate stacks for nMOSFET application”, Tech. Dig. IEEE International Electron Devices Meeting, p. 31-34, (2005).
[3.22] Y. Li and T. P. Ma, “A front-gate charge-pumping method for probing both interfaces in SOI devices”, IEEE Trans. Electron Devices, Vol. 45, pp. 1329-1335, (1998).
[3.23] W. H. Wu, B. Y. Tsui, M. C. Chen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “Spatial and energetic distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency capacitance-voltage measurement”, Appl. Phys. Lett. 89, 162911, (2006).
[3.24] C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, “Characterization and modeling of hysteresis phenomena in high-K dielectrics”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 737-740, (2004).
[3.25] F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, P. Masson, and R. Bouchakour, IEICE Trans. Electron. E88-C (2005) 829.
[3.26] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration”, IEEE Trans. Electron Devices, Vol. 41, pp. 2357-2362, (1994).
[3.27]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, D. Roan, P. J. Tobin, S. B. Samavedam, B. E. White, Jr., R. Gregory, and X.-D. Wang, “Impact of Zr addition on properties of atomic layer deposited HfO2”, Appl. Phys. Lett. 88, 222901, (2006).
[3.28] P. Masson, J. L. Autran, and J. Brini, “On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs”, IEEE Electron Device Lett., vol. 20, pp. 92-94, (1999).
[3.29] K. Irino, Y. Tamura, S. Ohkubo, T. Nakanishi, M. Shigeno, K. Hikazutani, M. Higashi, T. Fukuda, and K. Takasaki, “High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide”, VLSI Symp. Tech. Dig., pp.117-118, (1999).
[3.30] H. Yamashita, W. Mizubayashi, H. Murakami, and S. Miyazaki, in Int. Workshop on Gate Insulator, IWGI., pp. 224-225, (2001).
[3.31] W. L. Warren, J. Robertson, and J. Kanicki, “Si and N dangling bond creation in silicon nitride thin films”, Appl. Phys. Lett., 63, 2685, (1999).
[3.32] H. Momida, T. Hamada, T. Yamamoto, T. Uda, N. Umezawa, T. Chikyow, K. Shiraishi, and T. Ohno, “Effects of nitrogen atom doping on dielectric constants of Hf-based gate oxides”, Appl. Phys. Lett., 88, 112903, (2006).
[3.33] S. Zafar, C. Cabral, Jr., R. Amos, and A. Callegari, “A method for measuring barrier heights, metal work functions and fixed charge densities in metal/SiO2/Si capacitors”, Appl. Phys. Lett., 80, 4858, (2002).
[3.34] H. C. Wen, R. Choi, G. A. Brown, T. Bscke, K. Matthews, H. R. Harris, K. Choi, H. N. Alshareef, H. Luan, G. Bersuker, P. Majhi, D. L. Kwong, and B. H. Lee, “Comparison of effective work function extraction methods using capacitance and current measurement techniques”, IEEE Electron Device Lett., vol. 27, pp. 598-601, (2006).
[3.35] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application”, VLSI Symp. Tech. Dig., pp. 56-57 (2004).
[3.36] W. Mizubayashi, N. Yasuda, H. Ota, H. Hisamatsu, K. Tominaga, K. Iwamoto, K. Yamamoto, T. Horikawa, T. Nabatameand and A. Toriumi, “Carrier separation analysis for clarifying leakage mechanism in unstressed and stressed HfAlOx /SiO2/ stack dielectric layers”, IEEE International Reliability Physics Symp. pp. 188-193, (2004).
[3.37] C. H. Liu, M. T. Lee, C. Y. Lin, J. Chen, Y. T. Loh, F. T. Liou, K. Schruefer, Anastasios, A. Katsetos, Zijian Yang, N. Rovedo, T. B. Hook, Clement Wann and T. C. Chen, Jpn. J. Appl. Phys. 41, 2423 (2002).
[3.38] V. Narayanan, K. Maitra, B. P. Linder, V. K. Paruchuri, E. P. Gusev, P. Jamison, M. M. Frank, M. L. Steen, D. La Tulipe, J. Arnold, R. Carruthers, D. L. Lacey, and E. Cartier, “Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks”, IEEE Electron Device Lett., 27, pp. 591-594, (2006).
[3.39] G. Ribe, M. Miiller, S. Bruyere, D. Roy, M. Denais, V. Huard, T. Skotnicki, and G. Ghibaudo, “Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques”, Proceeding IEEE European Solid-State Device Research Conference, pp. 89-92, (2004).
[3.40] W. H. Wu, B. Y. Tsui, M. C. Chen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High-κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method”, IEEE Trans. Electron Devices, Vol. 54, pp. 1330-1337, (2007).
[3.41] R. Puthenkovilakam, M. Sawkar, and J. P. Chang, “Electrical characteristics of postdeposition annealed HfO2 on silicon”, Appl. Phys. Lett. 86, 202902 (2005).
[3.42] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, “Characterization of the VT-instability in SiO2/HfO2 gate dielectrics”, IEEE International Reliability Physics Symp., pp. 41-45, (2003).
[3.43] J. C. Liao, Y. K. Fang, Y. T. Hou, W. H. Wu, C. L. Hung, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, “Observations in trapping characteristics of positive bias temperature instability on high-k/metal gate n-type metal oxide semiconductor field effect transistor with the complementary multi-pulse technique”, Thin Solid Films, 516, pp. 4222-4225, (2008).
[4.1] M. Casse, L. Thevenod, B. Guillaumot, L. Tosti, F. Martin, J. Mitard, O. Weber, F. Andrieu, T. Ernst, G. Reimbold, T. Billon, M. Mouis, and F. Boulanger, “Carrier transport in HfO2/metal gate MOSFETs: physical insight into critical parameters” IEEE Trans. Electron Device, Vol. 53, no. 4, pp.759-768, (2006).
[4.2] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k dielectrics reliability issues” IEEE Trans. Device and Materials Reliability, Vol. 5, pp. 5-19, (2005).
[4.3] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks” IEEE Trans. Device and Materials Reliability, Vol. 5, pp. 45-64, (2005).
[4.4] M. Gurfinkel, J. S. Suehle, J. B. Bernstein, and Yoram Shapira, “Enhanced gate induced drain leakage current in HfO2 MOSFETs due to remote interface trap-assisted tunneling”, Tech. Dig. IEEE International Electron Devices Meeting, S29-4, (2006).
[4.5] R. I. Hegde, D. H. Triyoso, P. J. Tobin, S. Kalpat, M. E. Ramon, H.-H. Tseng, J. K. Schaeffer, E. Luckowski, W. J. Taylor, C. C. Capasso, D. C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. B. La, E. Hebert, R. Cotton, X-D. Wang, S. Zollner, R. Gregory, D. Werho, R. S. Rai, L. Fonseca, M. Stoker, C. Tracy, B. W. Chan, Y. H. Chiu, and B. E. White Jr., “Microstructure Modified HfO2 Using Zr Addition with TaxCy Gate for Improved Device Performance and Reliability”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 696-699, (2005).
[4.6] Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen and M. S. Liang, “High Performance Tantalum Carbide Metal Gate Stacks for nMOSFET Application”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 31-34, (2005).
[4.7] P. F. Hsu, Y. T. Hou, F. Y. Yen, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, J. M. Chiou, K. M. Yin, J. J. Lee, R. L. Hwang, Y. Jin, S. M. Chang, H. J. Tao, S. C. Chen, M. S. Liang, and T. P. Ma, “Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application”, VLSI Symp. Tech. Dig., pp. 14-15, (2006).
[4.8] F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, P. Masson, and R. Bouchakour, “Characterization and modeling of gate-induced-drain-leakage” IEICE Trans. Electron., pp. 829-836, (2005).
[4.9] Tahui Wang, Tse-En Chang, Lu-Ping Chiang, Chi-Hung Wang, Nian-Kai Zous, and Chimoon Huang, “Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique” IEEE Trans. Electron Device, Vol. 45, pp. 1511-1517, (1998).
[4.10] Tse-En Chang, Chimoon Huang, and Tahui Wang, “Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET’s” IEEE Trans. Electron Device, Vol. 42, pp. 738-743, (1995).
[4.11] Yujun Li and T.P. Ma, “Suppression of geometric component of charge-pumping current in SOI/MOSFETs”, VLSI Symp. Tech. Dig., pp. 144-148, (1995).
[4.12] W. H. Wu, B. Y. Tsui, M. C. Chen, Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, “Spatial and energetic distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency capacitance-voltage measurement” Appl. Phys. Lett., Vol.89, 162911, (2006).
[4.13] D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, D. Roan, P. J. Tobin, S. B. Samavedam, and B. E. White, Jr., “Impact of Zr addition on properties of atomic layer deposited HfO2”, Appl. Phys. Lett., Vol. 88, 222901, (2006).
[4.14] S. A. Krishnan, M. A Quevedo-Lopez, R. Choi, P. D. Kirsch, C. Young, R. Harris, J. J. Peterson, Hong-Jyh Li, Byoung Hun Lee, and J. C. Lee, “Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks”, IEEE International Integrated Reliability Workshop Final Report, pp. 89-90, (2005).
[4.15] C. H. Ko, C. H. Ge, C. C. Chen, W. Y. Teo, H. N. Lin, H. W. Chen, C. W. Kuo, M. T. Yang, D. Y. Chen, C. Y. Fu, W. C. Lee, “Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications”, Tech. Dig. IEEE International Electron Devices Meeting pp. 273-276, (2007).
[4.16] M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y Tainaka, “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics”, IEEE Trans. Electron Devices, Vol. 51, pp. 440-443, (2004).
[4.17] J. C. Liao, Y. K. Fang, Y. T. Hou, W. H. Tseng, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, “Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs”, IEEE Electron Device Lett., Vol. 29, pp. 509-511, (2008).
[4.18] “Physics of Semiconductor Devices”, S.M. Sze, 2nd ed., NY, Wiley, (1981).
[4.19] J. Bardeen and W. Shockley, “Deformation Potentials and Mobilities in Non-Polar Crystals”, Phys. Rev., Vol. 80, pp.72, (1995).
[4.20] G. A. M. Hurkx, D. B. M. Klaassen, M. P. G. Knuvers, and F. G. O'Hara, “A New Recombination Model Describing Heavy Doping Effects and Low Temperature Behavior”, Tech. Dig. IEEE International Electron Devices Meeting, pp.307-310, (1989).
[4.21] Y. T. Hou, M. F. Li, H. Y. Yu, Y. Jin, and D. L. Kwong. “Quantum Tunneling and Scalability of HfO2 and HfAlO Gate Stacks”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 731-734, (2002).
[4.22] H. Yu, Y. T. Hou, M. F. Li, and D. L. Kwong, “Investigation of Hole-Tunneling Current Through Ultrathin Oxynitride/Oxide Stack Gate Dielectrics in p-MOSFETs”, J. Appl. Phys., Vol. 49, 1158, (2002).
[5.1] D. K. Schroder and J. A. Babcock, “Negative Bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, J. Appl. Phys., Vol. 94, no. 1, pp. 1-18, (2003).
[5.2] I. -W. Wu, W. B. Jackson, T. -Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing”, IEEE Electron Device Lett., Vol. 11, no. 4, pp. 167-170, (1990).
[5.3] C. E. Blat, E. H. Nicollian, and E. H. Poindexter, “Mechanism of negative bias- temperature instability”, J. Appl. Phys., Vol. 69, no. 3, pp. 1712-1720, (1991).
[5.4] K. Okuyama, K. Kubota, T. Hashimoto, S. Ikeda, and A. Koike, “Water-related threshold voltage instability of polysilicon TFTs”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 527-530, (1993).
[5.5] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M. Ashida, T. Muragishi, and T. Nishimura, “Negative bias temperature instability in poly-Si TFTs”, VLSI Symp. Tech. Dig., pp. 29-30, (1993).
[5.6] C. Y. Chen, J. W. Lee, S. D. Wang, M. S. Shieh, P. H. Lee, W. C. Chen, H. Y. Lin, K. L. Yeh, and T. F. Lei, “Negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors” IEEE Trans. Electron Device, Vol. 53, no. 12, pp. 2993-3000, (2006).
[5.7] A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, “Recent issues in Negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxtion”, IEEE Trans. Electron Device, Vol. 54, no. 9, pp. 2143-2154, (2007).
[5.8] Y. Mitani, “Influence of Nitrogen in ultra-thin SiON on Negative bias temperature instability under AC stress”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 5.4.1, (2004).
[5.9] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 14.4.1, (2003).
[5.10] S. Maeda, S. Maegawa, T. Ipposhi, H. Kuriyama, M. Ashida, Y. Inoue, H. Miyoshi, and A. Yasuoka, “An analytical method of evaluating variation of the threshold voltage shift caused by the Negative-bias temperature stress in poly-Si TFT’s”, IEEE Trans. Electron Device, Vol. 45, no. 1, pp. 165-172, (1998).
[5.11] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors”, J. Appl. Phys., Vol. 53, no. 2, pp. 1193-1202, (1982).
[5.12] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistor”, IEEE Trans. Electron Devices, Vol. 36, no. 9, pp. 1915-1922, (1989).
[5.13] T. J. King, M. G. Hack, and I. W. Wu, “Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors”, J. Appl. Phys., Vol. 75, no. 2, pp. 908-913, (1994).
[5.14] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou, “Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures”, IEEE Trans. Electron Devices, Vol. 39, no. 3, pp. 598-606, (1992).
[5.15] M. D. Jacunski, M. S. Shur, and M. Hack, “Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFT’s”, IEEE Trans. Electron Devices, Vol. 43, no. 9, pp. 1433-1440, (1996).
[5.16] S. P. Voinigescu, K. Iniewski, R. Lisak, C. A. T. Salama, J.-P. Noel, and D. C. Houghton, “New technique for the characterization of Si/SiGe layers using heterostructure MOS capacitors”, Solid-State Electron., Vol. 37, pp. 1491-1501, (1994).
[5.17] S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, L. S Driscoll, and A. G. O’Neil, “C-V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design”, Semicond. Sci. Tech., Vol. 18, pp. 738-744, (2003).
[5.18] M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectron. Reliab., Vol. 45, no. 1, pp. 71-81, (2005).
[5.19] A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, A. Varghese, R. B. Khamankar, and S. Krishnan, “Material dependence of hydrogen diffusion: Implications for NBTI degradation”, Tech. Dig. IEEE International Electron Devices Meeting, pp. 688-691, (2005).
[5.20] M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, and A. Bravaix, “Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide”, IEEE Trans. Device and Materials Reliability, Vol. 4, no. 4, pp. 715-722, (2004).
[5.21] B. Kaczer, V. Arkhipov, R. Degraeve, N. Collaert, G. Groeseneken, and M. Goodwin, “Disorder controlled kinetics model for negative bias temperature instability and its experimental verification”, IEEE International Reliability Physics Symp., pp. 381-387, (2005).