在本論文中，我們利用超高真空化學氣相沉積法(UHVCVD)，成長矽鍺P型金氧半場效電晶體 (SiGe PMOSFET)，並且研究鍺含量變化對於元件電特性及1/f雜訊之影響。
因為能帶分離及等效質量下降，壓縮應變矽鍺可以提高電洞的移動率，因此可以將它運用於矽基金氧半場效電晶體。由實驗結果證實，應變矽鍺P型金氧半場效電晶體在轉導最大值、轉導半高寬、驅動電流的表現均比純矽金氧半場效電晶體來的好。另外我們也發現應變矽鍺P型金氧半場效電晶體也比純矽金氧半場效電晶體遭遇到較少的短通道效應。
最後，我們觀察矽鍺P型金氧半場效電晶體的1/f雜訊機制。由於應變矽鍺P型金氧半場效電晶體的電洞大部分侷限在遠離矽和二氧化矽界面的矽鍺通道而接觸到較少的缺陷，因此在1/f雜訊表現方面比純矽金氧半場效電晶體還要小。此外在強反轉區時，隨著鍺含量上升，使得1/f雜訊表現由原本的載子變動理論轉變為移動率變動理論。

In this thesis, the SiGe PMOSFET structures grown by ultra high vacuum chemical vapor deposition (UHVCVD) are fabricated. DC characteristics and 1/f noise analysis for different Ge content in the SiGe channel have been demonstrated.
Introduction of compressively strained-SiGe layer into Si-based device is attributed to the fact that hole mobility can be enhanced due to energy band splitting and the reduction of effective mass. Experimental results show that strained-SiGe PMOSFETs enhance device performance in transconductance (gm) max, FWHM of gm, driving current and etc. Moreover, we also found that strained-SiGe PMOSFETs suffer from less short channel effect (SCE) than Si control counterparts.
Finally, the 1/f noise mechanism observed in strained-SiGe device is presented. Compared to Si control devices, strained-SiGe devices exhibit lower 1/f noise level due to holes in strained-SiGe devices are mainly confined in SiGe channel away from Si/SiO2 interface where many defects and traps are located. Moreover, 1/f noise behavior changes gradually from carrier number fluctuations to mobility fluctuations as Ge content increases at strong inversion region.

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