在本論文中，我們探討了先進製程，具有淺溝槽隔離( STI) 結構的p 型通道橫向擴散金氧半場效電晶體(LDMOS)，受熱載子影響產生的退化及其機制。
首先，我們會解釋高壓元件目前被廣泛應用的原因，並比較LDMOS 電晶體與一般低壓MOS 電晶體在結構上的差異。同時也介紹LDMOS 電晶體的優點及缺點。由於元件是在高功率環境下操作，熱載子可靠度將成為討論這類元件的重要議題。
接著，我們會仔細描述實驗中所使用的元件結構，並介紹元件參數的量測方法。一些元件的基本特性包括汲極電流對閘極電壓的特性曲線 (Id-Vg)、汲極電流隨汲極電壓的改變 (Id-Vd) 和靜態崩潰電壓(BVoff)，都會加以量測。
在 stress 期間，最大轉移電導(Gmmax)、臨界電壓(VT)、導通電阻(Ron)和線性區汲極電流(Idlin)等參數的退化情形都會受到檢視。在這些參數中，線性區汲極電流的退化最為明顯。我們發現電流在一開始會快速的增加，經過一段時間的stress後，電流會逐漸下降。針對這樣的變化情形，我們利用charge pumping 量測和電腦輔助模擬(TCAD)來加以分析。由分析結果顯示，線性區汲極電流的退化在初期主要受到電子注入與捕捉(Qot)的影響而增加，然而隨著stress 時間越久，介面能態(Nit)會持續變多因而導致後半段的電流下降。
在最後的部份，我們利用相同結構的元件，進一步探討不同的stress 電壓對線性區汲極電流改變的影響。實驗結果發現，電流退化的現象會隨著stress電壓不同而有所區別。根據charge pumping 和TCAD 模擬結果，我們加以確認電流的退化機制。除此之外，實驗中也發現閘極電流(Ig)與線性區汲極電流的初期退化似乎有相關性，因此我們可以考慮利用閘極電流作為評估元件初期退化的指標。

In the thesis, hot-carrier-induced degradation and mechanisms in advanced p-type lateral diffused metal-oxide-semiconductor (LDMOS) transistors with STI structure are investigated.
First, we will explain why the high-voltage device is widely used now, and then compare the structure difference between LDMOS transistor and normal low-voltage MOS. The advantage and drawback of LDMOS transistors would be introduced. Because of high power operation, hot-carrier reliability may become a serious concern for such a device.
Next, we will describe the device structure used in the study and introduce the measurement methodology of device parameters. Device characteristics including Id-Vg, Id-Vd, and BVoff in the fresh state are measured and presented.
The degradation of some parameters such as Gmmax, VT, Ron and Idlin are monitored during hot-carrier stress experiment. Among the parameters, Idlin degradation is the severest. It is found that Idlin increases abruptly at the beginning, after a certain stress time, Idlin become decreasing. According to both charge pumping measurement and TCAD simulation results, we could verify such an anomalous Idlin degradation is dominated by electron trapping (Qot) in the first stage. As stress time increases, interface states (Nit) would keep increasing and result in a decrease in Idlin.
In the final part, we will further investigate the effects of stress voltage on Idlin shift with the same device structure. It is found that Idlin saturation phenomena are different under various stress conditions. Based on charge pumping analysis and TCAD simulation results, the mechanisms responsible for Idlin degradation could be confirmed. Besides, the gate current is found to be correlated to initial shift of Idlin, and thus Ig might be a good monitor to judge the severity of initial Idlin shift in this pLDMOS device.

[1] C. Y. Tsai, et al., “16–60 V rated LDMOS show advanced performance inan 0.72 μm evolution BiCMOS power technology,” in IEDM Tech. Dig.,pp. 367-370 (1997).
[2] V. Parthasarathy, et al., “A 33 V, 0.25 mΩ*cm2 n-channel LDMOS in a 0.65 μm smart-power technology for 20-30 V operation,” in Proc. Int.Symp. Power Semiconductor Dev., pp. 61-64 (1998).
[3] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose, and T. Roggenbauer, “Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, (2001), pp. 403-406.
[4] S. Pendharkar, R. Pan, T. Tamura, B. Todd, and T. Efland, “7 to 30V state-of-art power device implementation in 0.25um LBC7 BiCMOS-DMOS process technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, (2004), pp. 419-422.
[5] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35μm BCD technology (BCD6),” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, (2000), pp. 323-326.
[6] A.W. Ludikhuize, M.Slotboom,A.Nezar, N.Nowlin, and R. Brock, “Analysis of hot-carrier-induced degradation and snapback in submicron 50 V lateral MOS transistors,” ISPSD, pp.53-56 (1997).
[7] S. Aresu, W. D. Ceuninck, G. V. D. bosch, G. Groeseneken, p. Moens, J. Manca, D.Wojciechowski, P.Gassot, “Evidence for source side injection hot carrier effects on lateral DMOS transistors,” Microelectronics & Reliability, vol.44, pp. 1621-1624 (2004).
[8] P.L.Hower,”Safe Operating Area-a New Frontier in LDMOS Design,” ISPSD,pp. 1-8 (2002).
[9] A. G. Sabnis, “VLSI reliability,” in VLSI Electronic Microstructure Science, vol. 22, Academic Press, New York, Chapter 6, 1990.
[10] C. Y. Chang and S. M. Sze, “ULSI Technology,” McGraw-Hill, New York, pp. 657-658, (1996).
[11] A. G. Sabnis, Ref. 10.
[12] J. Wiley and Genichi Taguchi, “The Mahalanobis-Taguchi strategy: a pattern technology system,” (2002).
[13] W. Sun, H. Wu, L. Shi, Y. Yi, and H. Li, “On-Resistance Degradations for Different Stress Conditions in High-Voltage pLEDMOS Transistor With Thick Gate Oxide,” IEEE Electron Device Letters, Vol. 28, No. 7, July 2007.
[14] H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, “Hot Carrier Stress Degradation Modes in p-type High Voltage LDMOS Transistors.”
[15] R. Y. Su, P. Y. Chiang, J. G., Tsung Y. Huang, C. L. Tsai, C. C. Chou,and C. M. Liu,” Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure,” IEEE Transactions on Electron Device, Vol. 55, No. 12, December 2008.
[16] J. F. Chen, Member, IEEE, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu,” On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region,” IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008.
[17] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu, “Mechanism and Modeling of On-Resistance Degradation in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors,” Japanese Journal of Applied Physics 48 (2009).
[18] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker “A Reliable Approach to Charge Pumping Measurements in MOS-Transistors,” IEEE Trans. Electron Devices, vol. 31, no. 1, pp. 42-53, Jan. 1984.
[19] Dieter K. Schroder, “Semiconductor Material and Device Characterization,” second edition.
[20] J. F. Chen, Member, IEEE, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu” Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009.