半導體製程日新月異，從130nm製程發展到28 nm，相對的積體電路線寬越來越窄，當元件縮小時對微影技術的解析度就需要變的高，製程挑戰也越來越嚴苛，維持晶圓表面的平坦化程度直接影響到微影製程，而化學機械研磨是最佳的平坦化製程。
本文於化學機械研磨製程之研究中，首先針對兩種研磨粒徑尺寸與軟硬的研磨墊，利用實驗計畫法探討磨壓力、研磨漿量跟氧化劑濃度對金屬薄膜、阻障層薄膜、氧化矽薄膜還有低介電材料移除率的影響。從分析結果中，發現比較特別的是低介電材質薄膜之移除率快慢跟粒徑大小是相反趨勢，並在軟墊上移除效率會比硬墊上快。
利用空白晶圓上的移除量，來比較金屬層移除率跟氧化層移除率之間的選擇比關係，並藉由空白晶圓上的選擇比，實際應用在圖案晶圓上進而判斷該研磨條件變化對最終研磨平坦化的影響，並觀察在不同選擇比對100m 線寬跟9m 線寬的金屬損失量，不論在軟墊跟硬墊上選擇比必須要小於一，以避免研磨終止時，過渡研磨造成額外金屬層損失，造成銅線上嚴重碟深與介電層上的整體碟深。

關鍵字: 化學機械研磨、阻障層、平坦化、移除率、碟深、整體碟深。

Until now, leading enterprises (such as TSMC, IBM, Intel, and Samsung) still keep a growing number of investments in semiconductor technology upgrade and new technology development. As improvement of lithography technology and increasing request of VLSI (very large-scale integration), advanced semiconductor electronic devices continue to shrink from 130nm, 90nm, 45nm to 28nm, even 14nm and wafer size is enlarged from 200mm to 300mm (450mm wafer is under evaluation). In order to get stable manufacture process of advanced nano-devices, global wafer plananzation would be the most important factor to achieve this target. Among plananzation methods, CMP (Chemical Mechanical Polishing/plananzation) process is well-known as the one to provide better manufacture control capabilities.
In metal CMP process, barrier slurry is responsible for Cu layer topography and defectivity which play an important role in manufacture yield and next Cu film stack. For barrier slurry components, colloidal silica particle providing mechanical force is critical to final polishing performance. This thesis focuses on Cu/barrier blanket wafers removal rate (RR) selectivity and pattern wafer topography of different particle size in barrier slurry.
Removal rate selectivity of different blanket wafers (including Cu, TEOS, TaN and Coral) is collected on soft/hard pads by DOE study (design of experiments). In this DOE, controlled factors are (1) different polishing down force (DF), (2) oxidant concentration (H2O2%) and (3) slurry flow (SF) amount. From polishing results, (1) Cu, TaN and TEOS RR would depend on particle size on both soft and hard pad; (2) low k film (Coral) RR is opposite to particle size and higher on soft pad under the same DF and SF.
After getting blanket wafer polishing performance, a correlation establishment between RR selectivity of blanket wafer and Cu loss amount of pattern wafer is the next step. For pattern wafer polishing, requested RR selectivity (Cu/barrier) ratio must be less than 1 on both soft and hard pads to avoid excess Cu loss. It means that Cu RR must be less than other barrier films (TEOS, Ta/TaN or Coral). For final pattern wafer evaluation, topography performance including dishing (100x100μm assay) and erosion (9x1μm assay) would be strongly related to the blanket wafer selectivity. Under the condition of the RR selectivity less than one, the higher selectivity (Cu/barrier) would obtain the higher dishing and performance.

Key Words: CMP (Chemical Mechanical Polishing), Barrier, Plananzation Efficiency, Removal Rate, Dishing, Erosion

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