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研究生: 范宇軒
Fan, Yu-Xuan
論文名稱: 94-GHz CMOS電容性交互耦合中和技術功率放大器與電感性回授技術之功率放大器及應用於毫米波射頻接收機低雜訊放大器之研製
Research on 94-GHz PAs Using Capacitive Cross-Coupling Neutralization and Inductive Feedback Neutralization Techniques and 94-GHz Low Noise Amplifier for Millimeter-Wave RF Receiver
指導教授: 張志文
Chang, Chih-Wen
共同指導教授: 黃尊禧
Huang, Tzuen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 中文
論文頁數: 96
中文關鍵詞: 94-GHzW-bandCMOS毫米波功率放大器低雜訊放大器
外文關鍵詞: CMOS, Millimeter-Wave (MMW), W-band, Low-noise amplifier (LNA), Neutrolization, Power amplifier (PA)
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  • 本論文晶片設計採用TSMC CMOS 90-nm製程,量測方面皆以on-wafer進行量測。論文第一部份為設計94-GHz CMOS電容性交互耦合中和技術功率放大器。,每級放大器皆使用電容性交互耦合中和技術提升隔離度及功率增益,輸入、輸出匹配以及各級放大器之級間匹配使用傳輸線製成之變壓器來完成匹配以及訊號的結合。
    論文第二部分為設計94-GHz CMOS電感性回授技術之功率放大器。使用四級共源級差動架構,前三級放大器使用電感性回授技術提升隔離度及功率增益,最後一級輸出級使用電容性交互耦合中和技術提升隔離度及功率增益。輸入、輸出匹配以及各級放大器之級間匹配使用傳輸線製成之變壓器來完成匹配以及訊號的結合。
    論文第三部份為研製設計一個應用於毫米波射頻接收機之94-GHz CMOS低雜訊放大器。低雜訊放大器採用共源極與共閘極形成疊接組態,再利用串接五級電路可將94-GHz的輸入訊號放大至一定的水準,而為了更有效抑制雜訊,本次設計分別在前兩級電路間加入雜訊匹配電感以達最佳化雜訊之功用。電路中之走線皆有透過適當彎折以達晶片面積之最佳利用,在佈局上皆採用M9當訊號線以減少訊號對基板的寄生電容所造成的損耗。

    This thesis presents the research on 94-GHz power amplifiers (PAs) using capacitive cross-coupling neutralization technique and inductive feedback neutralization technique and 94-GHz low noise amplifier for millimeter-wave RF receiver in 90-nm CMOS. The first part is to introduce the design of 94-GHz PA using capacitive cross-coupling neutralization. The PA constructed four stage amplifier, which each stage consists of common source (CS) topology with using push-pull configuration. The amplifier of each stage uses capacitive cross-coupling neutralization to improve the isolation and stability of the PA, meanwhile, the small-signal gain of the PA also advanced due to the neutralized capacitor. The PA featured with transformer (TF) by using transmission line (TL) to achieve power combining and matching network, including input matching, power matching and conjugate matching. The second part is to introduce the design of the 94-GHz PA using inductive feedback neutralization technique. This work also presents four- stage PA design, which each stage consists of CS topology with using differential configuration to improve the linearity and output power. The PA stage uses capacitive cross-coupling neutralization to improve the isolation, power gain and stability of the PA stage, excluding the PA stage, the others use inductive feedback neutralization by using the effect of resonator to improve the isolation and power gain. The PA also featured with TF by using TL to achieve power combining and matching network. The third part of the design is Low Noise Amplifier for millimeter-wave RF receiver in 90-nm CMOS. The LNA constructed five-stage amplifiers, which each stage consists of cascode topology to advance higher power gain and isolation. The first and second stage amplifier featured with noise improvement inductor to reduce the noise contribution from common gate (CG) transistor.

    第一章 緒論 1 1.1 研究動機與背景 1 1.2 文獻回顧 3 1.3 論文架構 4 第二章 功率放大器基本概念 6 2.1功率放大器重要參數 6 2.1.1輸出功率(output power) 6 2.1.2效率(efficiency) 6 2.1.3小訊號增益平坦度(small signal gain flatness) 8 2.1.4增益斜率(gain slope) 8 2.1.5線性度(linearity) 8 2.1.6調幅/調相(AM/PM)與調幅/調幅(AM/AM)轉換失真(distortion) 9 2.1.7穩定度(stability) 10 2.2 功率放大器基本介紹 12 2.2.1偏壓類型及操作模式 12 2.2.2驅動級線性度之設計考量 12 2.2.3匹配考量 13 2.3 功率結合器分析 13 2.3.1直接結合(direct combining) 14 2.3.2威爾金森功率分波/結合器(Wilkinson power divider/combiner) 14 2.3.3方向耦合器(Directional coupler) 15 2.3.4變壓器(Transformer) 15 第三章 94-GHz CMOS電容性交互耦合中和技術功率放大器 20 3.1 研究背景與動機 20 3.2 共源級、疊接架構、堆疊架構比較 22 3.3 電容性交互耦合中和技術簡介 23 3.3.1 電容性交互耦合中和技術之理論及推導 24 3.4 94-GHz CMOS電容性交互耦合中和技術功率放大器 28 3.4.1 規格探討 29 3.4.2 電路設計說明與考量 29 3.4.3設計流程總結 39 3.5 94-GHz CMOS電容性交互耦合中和技術功率放大器模擬測結果 41 3.5.1 模擬結果 41 3.5.2 量測結果 44 3.5.3 量測與模擬特性 46 3.6 結果與討論 47 第四章 94-GHz CMOS電感性回授技術之功率放大器 49 4.1 電感性回授技術簡介 49 4.1.1 電感性回授技術之理論及推導 50 4.2 94-GHz CMOS電感性回授技術之功率放大器 57 4.2.1 規格探討 58 4.2.2 電路設計說明與考量 59 4.2.3 設計流程總結 65 4.3 94-GHz CMOS電感性回授技術之功率放大器模擬與量測結果 67 4.3.1 模擬結果 67 4.3.2 量測結果 70 4.4 結果與討論 72 第五章 應用於毫米波射頻接收機之94-GHz CMOS低雜訊放大器 74 5.1 研究動機 74 5.2 雜訊降低架設計流程總結構以及選擇 75 5.2.1 雜訊降低架構原理及分析 76 5.3 規格探討與架構評估 77 5.3.1 電路設計與考量 77 5.3.2 設計流程總結 81 5.4應用於毫米波射頻接收機之94-GHz CMOS低雜訊放大器模擬與量測結果83 5.4.1 模擬結果 83 5.4.2 量測結果 87 5.5 結果與討論 89 第六章 結論 90 參考文獻 92 圖目錄 圖1.1 毫米波應用頻譜示意圖 1 圖 1.2 電磁波在大氣層中的衰減圖 2 圖 2.1 放大器功率輸入輸出關係圖 7 圖 2.2 調變訊號經功率放大器後輸出頻譜示意圖 8 圖2.3 AM-AM及AM-PM DISTORTION 9 圖2.4 AM-AM及AM-PM所產生的IM3 9 圖2.5 兩級放大器級間穩定度模擬設置方法 10 圖2.6 奇模穩定度分析 11 圖2.7 奇模半電路穩定度分析 11 圖2.8 三級功率放大器示意圖 13 圖2.9直接功率結合示意圖 14 圖2.10 威爾金森功率結合放大器電路圖 14 圖2.11 平衡式放大器示意圖 15 圖2.12 推拉式放大器電路圖 16 圖2.13 分布式主動變壓器 17 圖2.14 分布式主動變壓器等效電路示意圖 17 圖2.15 並聯式功率結合變壓器 18 圖2.16 電流結合變壓器 19 圖3.1 94-GHz非對稱式可升降頻雙平衡混頻器射頻收發機架構圖 21 圖3.2 電晶體寄生電容示意圖 23 圖3.3 電容性交互耦合中和架構 24 圖3.4 中和電容之差動對小訊號分析24 圖3.5 Y11示意圖 25 圖3.6 Y12示意圖 25 圖3.7 Y21示意圖 25 圖3.8 Y22示意圖 25 圖3.9 電路架構圖 28 圖3.10 (a) 直接功率結合布局圖 (b) 功率結合之MSG/MAG示意圖 30 圖3.11 輸出級架構圖 31 圖3.12 不同等效電容在94GHz對(a) MAG (b) K-Factor作圖 32 圖3.13 驅動級放大器架構圖 33 圖3.14 不同等效電容在94GHz對(a) MAG (b) K-Factor作圖 33 圖3.15 增益級放大器架構圖 34 圖3.16 不同等效電容在94GHz對(a) MAG (b) K-Factor作圖 34 圖3.17 各級電路之功率預算設計圖 (power design budget) 35 圖3.18 94-GHz CMOS電容性交互耦合中和技術功率放大器整體電路設計架構圖 35 圖3.19 (a) 振幅不平衡模擬圖 (b) 相位不平衡模擬圖 (c) 變壓器雙端轉單端示意圖 36 圖3.20 變壓器示意圖 37 圖3.21 94-GHz CMOS電容性交互耦合中和技術功率放大器(a) 佈局圖 (b) 照相圖 40 圖3.22 94-GHz CMOS電容性交互耦合中和技術功率放大器模擬特性圖 (a)輸入輸出返回損耗及小訊號增益 (b)功率增益、PAE與Pout (c)整體穩定度 (d)級間穩定度 43 圖3.23 (a) S參數量測架設示意圖 (b) 大訊號量測架設示意圖 44 圖3.24 94-GHz CMOS電容性交互耦合中和技術功率放大器量測特性圖。 (a)輸入輸出返回損耗及小訊號增益 (b) Pout、Gain與PAE (c)整體穩定度 45 圖4.1 電感性回授之示意圖 50 圖4.2 (a) 電晶體小訊號模型圖 (b) 小訊號模型共振腔示意圖 50 圖4.3 Y11示意圖 51 圖4.4 Y12示意圖 52 圖4.5 Y21示意圖 53 圖4.6 Y22示意圖 54 圖4.7 電路示意圖 57 圖4.8 輸出級放大器架構圖 59 圖4.9 驅動級放大器架構圖 60 圖4.10 (a) 感值對應MAG模擬圖 (b) 感值對應K-Factor模擬圖 60 圖 4.11 電晶體並聯示意圖 61 圖4.12 (a) 電晶體並聯下感值對應MAG (b) 電晶體並聯下感值對應K-Factor 61 圖4.13 (a) 不同頻率下之電感值 (b) 不同頻率下電感寄生電阻 (c) 不同頻率下之品質因數 62 圖4.14 個級電路之功率預算設計圖(power design budget) 63 圖4.15 94-GHz CMOS電感性回授技術之功率放大器整體電路設計架構圖 63 圖4.16 變壓器示意圖 64 圖4.17 (a) 晶片佈局圖 (b) 晶片照相圖 66 圖4.18 94-GHz CMOS電感性回授技術之功率放大器模擬特性圖 (a) 輸入輸出返回損耗及小訊號增益 (b) Gain、PAE、Pout (c)整體穩定度 (d)、(e)、(f)各級之級間穩定度 69 圖4.19 (a) S參數量測架設示意圖 (b)大訊號量測示意圖 70 圖4.20 94-GHz CMOS電感性回授技術之功率放大器量測特性圖 (a) 輸入輸出返回損耗及小訊號增益 (b) Pout、Gain、PAE (c)整體穩定度 71 圖5.1 射頻接收機示意圖 74 圖5.2 (a) 疊接架構圖 (b) 共閘級電感回授技巧 (c) 電容交互耦合回授技巧 (d) 串接電感技巧 (e) 並接電感技巧 75 圖5.3 級間雜訊匹配圖 76 圖5.4 (a) 不同尺寸下電流密度對應MAG與NF圖 (b) W=24um下VGS對應MAG與NF圖 77 圖5.5 低雜訊放大器電路圖 78 圖5.6 雜訊匹配電感布局圖 78 圖5.7 不同感值下頻率對應雜訊模擬圖 79 圖5.8 不同Q值下頻率對應雜訊模擬圖 80 圖5.9 (a) 晶片布局圖 (b) 晶片照相圖 82 圖5.10 低雜訊放大器電路模擬特性圖 (a) S-parameter (b) IP1dB (c) IIP3 (d) 整體電路穩定度 (e) NF 84 圖5.11 低雜訊放大器電路級間穩定度模擬特性圖 86 圖5.12 低雜訊放大器電路量測特性圖 (a) S-parameter (b) 整體電路穩定度(c) IP1dB (d) NF 88   表目錄 表2.1 功率放大器之類別與特性表 12 表2.2 變壓器功率結合示意圖 16 表2.3 串聯式與並聯式功率結合變壓器比較 18 表2.4 電壓與電流結合變壓器比較表 19 表3.1 CS、Cascode、Stacked 架構比較表 22 表3.2 電容性交互耦合中和技術功率放大器設計規格表 29 表3.3 在94GHZ頻率操作下不同總寬度72-88um之負載拉移模擬 30 表3.4變壓器參數表 38 表3.5 功率放大器量測與模擬特性總表 46 表3.6 功率放大器參考文獻規格比較列表(多路功率結合) 47 表3.7 功率放大器參考文獻規格比較列表(一路) 48 表4.1 電感性回授之功率放大器設計規格表 58 表4.2 變壓器參數表 64 表4.3 功率放大器參考文獻規格比較列表(多路功率結合) 72 表4.4 功率放大器參考文獻規格比較列表(一路) 73 表5.1 低雜訊放大器參考文獻規格比較列表 89

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