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研究生: 王景新
Wang, Jing-Xin
論文名稱: 平行化H.264/AVC編碼器於分散式共用記憶體系統
Parallel H.264/AVC Rate-Distortion Optimization Baseline Profile Encoder on Distributed Shared Memory System
指導教授: 蘇文鈺
Su, W. Y. Alvin
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 83
中文關鍵詞: H.264/AVC編碼器位元率失真度最佳化共用記憶體系統平行切片演算法
外文關鍵詞: H.264/AVC encoder, rate-distortion optimization, distributed shared memory system, parallel slice scheme
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  • H.264/AVC壓縮標準提供了相當多的新的壓縮元件來提升影片壓縮品質,但是這些元件也造成了計算量的提升,其中支援位元率失真度最佳化的H.264/AVC編碼器更需要大量的計算來得到更多的壓縮品質,為了提升壓縮速度,平行化H.264/AVC編碼器為其中一種選擇。然而H.264/AVC編碼器需要相當多的參考資料於相鄰的區塊(macroblock),因此H.264/AVC編碼器並不適合於平行化的實作,尤其是應用於分散式共用記憶體系統。在叢集式電腦系統中,分散式共用記憶體系統提供了虛擬共用記憶體的機制,讓程式設計者能夠輕易的撰寫平行化程式,但是分散式共用記憶體系統的共用記憶體大小及共用資料傳輸次數深深影響著平行化的效能,為了提升平行化的效能,我們提出了一個平行化H.264/AVC編碼器的架構來減少參考資料傳輸的次數,然後於這個平行化架構下提出三種平行H.264/AVC編碼器的演算法,分別為平行切片演算法(parallel slice scheme,PSS)、平行多張參考影像演算法(Parallel Multiple Reference Frames Scheme,PMRFS)及平行塊模式演算法(Parallel Block Mode Scheme,PBM),將這三種演算實作於分散式共用記憶體系統,平行切片演算法(parallel slice scheme)為三種演算法中速度提升效能最高的演算法,然而這個平行化H.264/AVC編碼器架構及平行切片演算法會使得影片壓縮率下降,接著依據平行切片演算法特性提出改良的平行化H.264/AVC編碼器架構及改良的平行切片演算法(PSS_M)來提升影片壓縮率,再將改良的平行切片演算法實作於分散式共用記憶體系統。本論文實驗的分散式共用記憶體系統使用了5台電腦,每台電腦有兩個雙核心處理器,在影片壓縮率部分,使用改良的平行切片演算法的影片壓縮壓縮率於移動較少的影像影響相當微小,例如:Akiyo;在速度提升的部分,最大壓縮速度提升的比率為4.22在n=5/p=1(由5台電腦執行,每台電腦只使用一顆處理器),最後平行切片演算法結合wavefront order scheme (PSS_MW)也被實作於分散式共用記憶體系統,而使用的電腦數量為5與每台電腦使用4個處理器(n=5/p=4),PSS_MW的壓縮速度還可以再提升2.61倍。由於論文中提出了三種演算法速度提升及影像品質的結果,雖然改良的平行切片演算法提供了較佳的效能,但是這三種演算法之間為獨立演算法,如有更多台電腦的平行計算平台時,三種方法混合使用可能可以達到更佳的效果,此論文可以作為三種方法混和的參考。

    H.264/AVC video coding standard incorporates many coding tools into its design to improve its compression performance. In a H.264/AVC rate-distortion optimization (RDO) encoder, computation time is primarily spent on calculating the rate-distortion cost (RD) of choosing the best coding mode. Parallel computation is one of the methods to speed up the encoder. However, calculating the rate-distortion cost requires lots of reference data obtained from coded adjacent macroblocks. This is not a good property for any parallel computing strategy, especially for distributed shared memory (DSM) system. In a cluster computing system, DSM provides the virtual shared memory scheme to write the parallel program more easily. But the amount of transferring data and the frequency of transferring data on each computer affect the speedup. To gain more speedup, this thesis proposes a parallel H.264/AVC RDO encoder architecture to reduce the frequency of transferring reference data. Based on this architecture, three parallel computing schemes, including Parallel Slice Scheme (PSS), Parallel Multiple Reference Frames Scheme (PMRFS) and Parallel Block Mode Scheme (PBM) are proposed. Parallel slice scheme (PSS) outperforms other two schemes on a DSM system. However, the video quality would be decreased in our proposed parallel architecture with PSS. To improve more video quality, this thesis also proposes the modified parallel architecture and the modified PSS (PSS_M) based on PSS. PSS_M is run over a DSM system consisting of 5 PC computers (one master node with four slave processing nodes). Each computer has two dual-core processors. The difference in PSNR curve between PSS_M and H.264/AVC RDO encoder without parallelism is slight in slow motion sequence such as Akiyo. The maximum speedup of PSS_M is 4.22 in n=5/p=1 (five computers are used and each computer only uses one core). In addition, PSS_M combined with wavefront order scheme (PSS_MW) in n=5/p=4 had executed in this thesis. The maximum improvement in speedup in p=4 is 2.61. The video quality and speedup of our proposed three schemes are shown in this thesis. Although PSS_M obtains more coding efficiency than the other method, it is possible to combine three schemes to get more video quality and speedup when more number of the computers is used. This thesis provides a good reference for implementing the combined scheme.

    List of Tables 11 List of Figures 12 Chapter 1. Introduction 13 1.1. Motivation 15 1.2. Objective 16 1.3. Organization 16 Chapter 2. Previous Work 17 2.1. H.264/AVC Baseline Profile 17 2.1.1 Intra Prediction 19 2.1.2 Motion Vector Prediction 20 2.1.3 Context-based Adaptive Variable Length Coding (CAVLC) 22 2.1.4 Adaptive Deblocking Filter 23 2.2. Previous Parallel H.264/AVC Encoder Schemes 24 2.2.1. Independence Slice Scheme 24 2.2.2. Wavefront Order Scheme 25 2.3. Distributed Shared Memory System 27 Chapter 3. Parallel H264/AVC Encoder Architecture and Schemes 29 3.1. Parallel H.264/AVC Encoder Architecture 29 3.2. Parallel inter and intra prediction schemes 33 3.2.1. Intra Prediction 33 3.2.2. Inter Prediction 35 3.2.3. Decision Between Inter Mode and Intra Mode for A MB 40 3.2.4. Analysis of Shared Data Amounts for Inter Prediction Schemes 40 3.3. Simulation Result 42 3.3.1. Video Quality 42 3.3.2. Execution Time and Speedup 50 Chapter 4. Modified Parallel Slice Scheme 57 4.1. Modified Parallel H.264/AVC Encoder Architecture 57 4.2. Modified Parallel Slice Scheme 58 4.3. Multi-core environment 62 4.4. Experimental Results 64 4.4.1. Video quality 64 4.4.2. Execution Time and Speedup 68 Chapter 5. Conclusion and Future Work 73 5.1. Speedup 73 5.2. Video Quality 74 5.3. Many-core Processor 75 REFERNCES 77

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