進階加密標準(advanced encryption standard, AES)演算法，由比利時兩位密碼學家Joan Daemen和Vincent Rijmen所設計的Rijndael演算法獲選，並由美國國家標準與技術研究院(NIST)於2001年11月26日發布為有效的標準，爾後該演算法也成為現今最熱門、最普遍選擇使用的加密方式。隨著無線通訊技術的發展、5G網路的興起，在各個應用層面的資料產出速率都因而提升，而在大多數應用中，資料安全有一定的重要性，要在高資料傳輸速率的情況下仍將每筆資料安全加密，是現今面臨的挑戰。因此，如何實現兼具低成本與高資料傳輸速率的AES硬體電路，為本篇論文的研究目標。
本篇論文從AES演算法中，運算複雜度最高的位元組取代運算下手，並參考文獻引入GF((〖〖(2〗^2)〗^2)^2)複合域算術取代原先的伽羅瓦域數學運算，從原始數學式作化簡、整理並設計出硬體，並依據路徑延遲安插暫存器，使得時脈頻率提高。本篇論文實現於多款Xilinx Virtex 4-6系列的FPGA上與TSMC 90nm製程，並與文獻探討、比較，時脈頻率、面積、資料傳輸速率和面積使用效率這四項數據。英文摘要因篇幅有限，故僅提及本篇設計之S-box硬體電路，並與文獻比較。

To save the space, the English version only presents the VLSI architecture of the proposed S-box and inverse S-box, which are the most critical parts of the advanced encryption standard (AES). We employ the composite field arithmetic (CFA) to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is proposed to further enhance the area efficiency. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T. This amounts to a throughput of 92.64 Gbps for the AES encryption. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency.

[1] National Institute of Standards and Technology, ”Specification for the Advanced encryption Standard(AES)”, FIPS PUB197, November26, 2001.
[2] Singha, Th & Palathinkal, Roy & Ahamed, Rafi, “Implementation of AES Using Composite Field Arithmetic for IoT Applications” 2020 Third ISEA Conference on Security and Privacy (ISEA-ISAP), 2020.
[3] Janveja, Meenali & Paul, Bikram & Trivedi, Gaurav & Vijayakanthi, Gonella & Agrawal, Astha & Pidanic, Jan & Nemec, Zdenek, “Design of Efficient AES Architecture for Secure ECG Signal Transmission for Low-power IoT Applications” 2020 30th International Conference Radioelektronika (RADIOELEKTRONIKA), 2020.
[4] A. Kchaou, W. Youssef and R. Tourki, "Software Implementation of AES Algorithm on LEON3 Processor", 15th international conference on Sciences and Techniques of Automatic control & computer engineering-STA, 2014.
[5] R, Santhosh & Rudregowda, Shashidhar & M, Mahalingaswamy & S, Praveen & M, Roopa, “Design of High Speed AES System for Efficient Data Encryption and Decryption System using FPGA”, 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), 2018
[6] Shastry, P., Somani, N., Gadre, A., Vispute, B., Su- taone, M, “Rolled architecture based implementation of AES using T-Box”, IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 626-630 ,2012.
[7] ManjithB., C., “Improving overall parallelism in AES accelerator using BRAM and multiple input blocks” 2019 Innovations in Power and Advanced Computing Technologies, p.p. 1-5, 2019.
[8] X. Zhang and K. K. Parhi, "High-speed VLSI Architecture for the AES Algorithm", IEEE Trans. on VLSI Systems, vol. 12, no. 9, pp. 957-967, Sep. 2004.
[9] S. Oukili and S. Bri, "High speed efficient advanced encryption standard implementation", 2017 International Symposium on Networks Computers and Communications (ISNCC), pp. 1-4, 2017
[10] Kouzehzar, Hossein, Meisam Nesary Moghadam and Pooya Torkzadeh, “A High Data Rate Pipelined Architecture of AES Encryption/Decryption in Storage Area Networks”, Electrical Engineering (ICEE), pp. 23-28, Iranian Conference on 2018.
[11] A. Hodjat, W. Ingrid, "A 21.54 Gbits/s fully pipelined processor on FPGA" 12th Annual IEEE Symposium on Field Programmable Custom Computing Machines, pp. 308 - 309, April 2004.
[12] Y. Wang and Y. Ha, “High Throughput and Resource Efficient AES Encryption/Decryption for SANs” in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 1166–1169.
[13] Bin Liu and Bevan M. Baas, "Parallel AES encryption engines for many-core processor arrays", Computers IEEE Transactions on, vol. 62, no. 3, pp. 536-547, 2013.
[14] Punia, Dheeraj & Singh, Brahmjit, “Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture”, 2019 International Conference on Communication and Electronics Systems (ICCES), 2019.
[15] R. Ueno et al., "High Throughput/Gate AES Hardware Architectures Based on Datapath Compression" in IEEE Transactions on Computers, vol. 69, no. 4, pp. 534-548, 1 April 2020.
[16] Mathew, Sanu K., Farhana Sheikh, Michael Kounavis, Shay Gueron, Amit Agarwal, Steven K. Hsu, Himanshu Kaul, Mark A. Anders, and Ram K. Krishnamurthy. "53 Gbps Native GF(2^4)^2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors" IEEE Journal of Solid-State Circuits 46, no. 4 (2011): 767-776.
[17] Mathew, S., Satpathy, S., Suresh, V., et al, “340 mV–1.1 V, 289 Gbps/ W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2^4)^2polynomials in 22 nm tri-gate CMOS”, IEEE Journal of Solid-State Circuits 46, 2014, 50, (4), pp. 1048–1058.
[18] Landge, I. A. G. and Mishra, B, “Iterative architecture AES for secure VLSI based system design”, 2016 Symposium on Colossal Data Analysis and Networking (CDAN) ,pp. 1-4, 2016.
[19] C. Sangwan, C. Bhardwaj and T. Sikka, "VLSI Implementation of Advanced Encryption Standard", 2012 Second International Conference on Advanced Computing & Communication Technologies, pp. 412-418, 2012.
[20] Mui, Edwin NC and Custom, “Practical Implementation of Rijndael S-Box Using Combinational Logic”, Custom R&D Engineer Texco Enterprise Pvt.Ltd, 2007.
[21] Mostafa Abd-El-Barr and Amro Khattab, “An Efficient Pipelined Multiplicative Inverse Architecture for the AES Cryptosystem,” International Journal of Information and Electronics Engineering, Vol. 4, No. 2, March 2014.
[22] S. S. Priya, K. G. Das, N. M. SivaMangai and P. K. Kumar, "Multiplexer based high throughput S-box for AES application," 2015 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, 2015, pp. 242-247.
[23] Saurabh Kumar, V.K. Sharma and K. K. Mahapatra,“ Low Latency VLSI Architecture of S-box for AES Encryption,” in International Conference on Circuits, Power and Computing Technologies [ICCPCT-2013], pp. 694-698, 2013.
[24] M. M. Wong and M. L. D. Wong, "A High Throughput Low Power Compact AES S-box Implementation using Composite Field Arithmetic and Algebraic Normal Form Representation", 2nd Asia Symposium on Quality Electronic Design, 2010.
[25] M. Wong, M. Wong, A. Nandi and I. Hijazin, "Construction of optimum composite field architecture for compact high-throughput AES S-Boxes", IEEE Trans. On VLSI Systems, vol. 20, no. 6, pp. 1151-1155, June. 2012.
[26] A. Reyhani-Masoleh, M. Taha and D. Ashmawy, "New Low-Area Designs for the AES Forward, Inverse and Combined S-Boxes," in IEEE Transactions on Computers, vol. 69, no. 12, pp. 1757-1773, Dec. 2020.
[27] Yaoping Liu, Ning Wu, Xiaoqiang Zhang, Fang Zhou and Fen Ge, "A Compact Implementation of AES S-Box Using Evolutionary Algorithm", Chinese Journal of Electronics, vol. 26, no. 4, July 2017.
[28] D. Canright, “A very compact S-Box for AES”, 7th International Workshop on CHES, Springer-Verlag, LNCS, Vol.3659, pp.441–455, 2005.
[29] J. Wolkerstorfer, E. Oswald, and M. Lamberger, “An ASIC implementation of the AES S-boxes,” in Proc. RSA Conf., San Jose, CA, Feb. 2002, pp. 67–78.
[30] Vincent Rijmen, “Efficient Implementation of the Rijndael S-box”, Katholieke Universiteit Leuven, Dept. ESAT. Belgium.
[31] Z. Yuan, Y. Wang, J. Li, R. Li and W. Zhao, “FPGA based Optimization for Masked AES Implementation,” The 54th IEEE International Midwest Symposium on Circuits and Systems, Seoul, South Korea, pp. 1-4, 2011.
[32] J. Zeng, Y. Wang, C. Xu and R. Li, “Improvement on Masked S-box Hardware Implementation,” International Conference on Innovations in Information Technology, Abu Dhabi, United Arab Emirates, pp. 113- 116, 2012.
[33] N. D. Parmar and P. Kadam, “Pipelined Implementation of Dynamic Rijndael S-Box,” International Journal of Computer Applications, vol. 111, pp. 36-38, February 2015.
[34] R. R. Rachh, P.V. AnandaMohan and B.S.Anami, “High Speed S-box architecture for Advanced Encryption Standard,” IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application, Bangalore, India, pp. 1-6, 2011.
[35] C. Savalam and P. Korapati, “Implementation and Design of AES S-Box on FPGA,” International Journal of Research in Engineering and Science, vol.3, pp. 9-14, January 2015.
[36] N. Kamoun, L. Bossuet and A. Ghazel, “SRAM-FPGA Implementation of Masked S-Box Based DPA countermeasure for AES,” Third International Design and Test Workshop, Monastir, Tunisia, pp. 74-77, 2008.
[37] R. Bahram and R. Bahman, “Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA,” International Journal of Computer Network and Information Security, vol.5, pp. 41-48, January 2013.
[38] A. Reyhani-Masoleh, M. Taha, and D. Ashmawy, “Smashing the implementation records of AES S-box,” IACR Trans. Cryptographic Hardware Embedded Syst., vol. 2018, no. 2, pp. 298–336, May 2018. [Online].
[39] Y. Wang, A. Kumar and Y. Ha, “FPGA-based High Throughput XTSAES Encryption/Decryption for Storage Area Network,” International Conference on Field-Programmable Technology (FPT), IEEE, Shanghai, pp.268-271, 2014.
[40] K. Rahimunnisa, P. Karthigaikumar, S. Rasheed, J. Jayakumar and S. SureshKumar, “FPGA implementation of AES algorithm for high throughput using folded parallel architecture,” Security and Communication Network, vol.7, pp. 2225-2236, November 2014.
[41] V. K. Sharma, S. Kumar and K. K. Mahapatra, “Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC,” Journal of Circuits, Systems, and Computers, vol. 25, pp.1-29, May 2016.
[42] Q. Liu, Z. Xu and Y. Yuan, “High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion,” IET Computers & Digital Techniques, vol. 9, pp.175-184, May 2015.
[43] K. Rahimunnisa, P. Karthigaikumar, N.A. Christy, S.S. Kumar and J. Jayakumar, “Psp: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC,” Central European Journal of Computer Science, vol.3, pp.173-186, December 2013.
[44] Q. Liu, Z. Xu and Y. Yuan, “A 66.1 Gbps Single-pipeline AES on FPGA,” International Conference on Field-Programmable Technology (FPT), IEEE, Kyoto, pp.378-381, 2013.