URAM 是聯華電子 (UMC) 的專利製程其全名是 UMC 的 DRAM，它和其它邏輯 (Logic) 製程不同的地方是在一般通用製程 淺溝槽隔離 (Shallow Trench Isolation)的區域改用深溝式 (Deep Trench) 的製程作出深溝式 DRAM 電容。並將其整合在同一個晶粒 (Die) 上，URAM 製程，最主要的優勢是以系統單晶片 (System on Chip, SoC) 的概念將 DRAM 和 Logic 元件其整合在同一個 Die 上或是以 DRAM 取代部份的 SRAM，讓同一片大小相同的晶圓 (Wafer)產出更多的 Die 數，降低製造成本，進而讓電子產品可以更省電、體積變小、功能更強、電子產品售價更低廉。
但這種新開發的製程技術，從研發階段到合乎經濟效應的量產過程中，發現良率尚無法達到預期目標。根據故障分析 (Fault Analysis) 的資料顯示，製程缺陷 (Defect) 是目前影響良率最主要的因素。
本論文針對如何改善 URAM 製程的缺陷，進而提升良率 (Yield) 作深入的研究。方法是利用缺陷檢驗機台 (BDFINP) 和電子顯微鏡 (SEM) 找出缺陷的種類和來源，根據不同種類缺陷形成的機制，提出種種改善方案，並進而將製程最佳化。實驗結果，發現經過改善後的 URAM 新製程， 良率可提升到 94.9%，達到可量產的經濟效益。

URAM (UMC’s DRAM ) process with DRAM embed in Shallow Trench Insulation (STI) is a UMC’s patent technology. The URAM is based on Solution of Chip (SoC) idea and integrates Logic with DRAM in an identical die. Use of DRAM to replace of some SRAM can reduce die areas ,and thus increase die numbers in one wafer to reduce the production cost. Therefore, the URAM is smaller, faster, cheaper and more efficient than the general process one.
Even though, the principle and the mechanism of the new technology are feasible, but the yield does not meet yet in mass production. Therefore, a systematical research has been taken to improve the yield. According to the results of fault analysis, we found the key factor for the low yield is the existence of defects in process.
This paper reported of our studies in improving the URAM process, and to reduce defect and to promote URAM yield. Based on the analyses by BDFINP and SEM , the defect sources and types are identified firstly, and then the yield was improved with optimization methods . Experiment results showed the yield could be up to 94.9% with the optimized process , to meet the requirement of production.

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