在本論文中，針對不同製程的整合型高壓元件(包含橫向擴散金氧半電晶體(LDMOS)及汲極延伸式金氧半電晶體(DEMOS))，探討熱載子所導致元件特性退化之現象及機制。
對於採用0.35微米製程之LDMOS電晶體，當元件被強迫操作在不同閘極偏壓下時，針對熱載子所引發導通電阻退化之異常現象做分析。導通電阻之退化是由於在N-漂移區中介面能態之產生所導致。再者，對於被強迫操作在中閘極及高閘極偏壓下之元件，雖然基板電流在高閘極偏壓下較大，其導通電阻之退化幾乎相同。造成導通電阻的退化大小和基板電流之間無任何關係之現象是綜合兩個因素之結果:撞擊游離率 (impact ionization rate)及介面能態產生之效率。此外，元件飽和電流之偏移可由底下兩個相互競爭之機制來決定。一個為在N-漂移區中介面能態之產生，另一個為在通道區域中介面能態之產生。前者會導致飽和電流的異常上升，而後者會使得飽和電流下降。嚴重之介面能態在N-漂移區之產生是造成飽和電流異常上升之主要機制。
對於採用0.25微米製程之DEMOS電晶體，當元件被強迫操作在高閘極及高汲極偏壓下，臨界電壓偏移得相當嚴重但是導通電阻之退化卻相當小。大量的熱電子在靠近汲極端通道區之閘極氧化層中注入及補捉被證實為造成嚴重臨界電壓偏移之機制。當元件被強迫操作在較高的閘極偏壓及較高的汲極偏壓下，其臨界電壓之退化會更嚴重，分別是因為在汲極端通道區附近之垂直電場變大及撞擊游離化上升所導致。另外，元件之臨界電壓退化隨時間增加有不正常上升之現象，此現象是由於撞擊游離化隨時間會越來越大所導致，而撞擊游離化會變大是歸因於被補捉在通道區中之大量負電荷。再者，也探討了通道長度的效應對熱載子所造成退化之影響。雖然導通電阻退化在長通道之元件中被改善，但元件之臨界電壓偏移卻變得較嚴重。對於長通道之元件，此非預期中之結果可以由消除克爾克效應(Kirk effect)所伴隨通道區中垂直電場之上升來解釋。
對於採用0.18微米製程之DEMOS電晶體，根據實驗數據及模擬之結果，熱載子所引發在閘極覆蓋STI區域中介面能態之產生是造成元件參數退化之主因。此外，元件飽和電流在破壞性量測後退化得相當嚴重，並且退化大小和導通電阻之退化相當接近。當元件被操作在高閘極偏壓下準飽和效應(quasi-saturation)之發生是造成嚴重飽和電流退化之主因。
最後，針對0.35微米製程之P型DEMOS電晶體其熱載子所造成退化之現象做探討。當閘極偏壓在第二個基板電流峰值時，元件會有最大之退化。熱載子所引發之介面能態在通道區之產生會導致臨界電壓之偏移。在閘極控制區外之漂移區中負電荷之產生，使得線性區電流在破壞性量測實驗一開始時之上升，然而在閘極控制區下之漂移區中介面能態之產生將導致在破壞性量測時間較長時，線性區電流偏移會有轉向之現象。

In this dissertation, phenomena and mechanisms of hot-carrier-induced degradation in integrated high-voltage MOS devices (including laterally diffused metal-oxide-semiconductor (LDMOS) transistors and drain-extended MOS (DEMOS) transistors) fabricated with various technologies are studied.
For the 0.35μm LDMOS transistors, hot-carrier-induced anomalous on-resistance (Ron) degradation for the device stressed under different gate voltage (Vg) is analyzed. Ron degradation is caused by interface state generation (ΔNit) in the N- drift region. Moreover, Ron degradation is almost identical for the devices stressed medium Vg and high Vg though bulk current (Ib) is much greater at high Vg bias. Such an Ib independent Ron degradation is the consequence of two combined factors: impact ionization (II) rate and Nit generation efficiency. Besides, the shift of saturation-region drain current (Id(sat)) can be determined by the following two competing mechanisms. One is the ΔNit in the N- drift region, and the other is the ΔNit in the channel region. The former mechanism results in the anomalous increase of Id(sat), while the latter
mechanism causes the Id(sat) to decrease. Significant ΔNit in the N- drift region is the main mechanism responsible for the anomalous increase of Id(sat).
For the 0.25μm DEMOS transistors, severe threshold voltage shift (ΔVT) but small Ron degradation is found when the device is stressed under high Vg and high Vd. Significant hot-electron injection and trapping in gate oxide above drain-side of channel region is identified to be the mechanism for severe ΔVT. The greater ΔVT under higher Vg and higher Vd stressing are attributed to larger vertical electric field (Ey) and larger II rate near the drain-side of channel region, respectively. In addition, abnormal increase of ΔVT is caused by the enhanced II rate owing to the presence of large amount of negative oxide charge (ΔNot) in channel region. Furthermore, effect of channel length (Lch) on hot-carrier-induced degradation is also investigated. Although Ron degradation is improved in longer Lch device, ΔVT is greater. Such a result can be explained by the enhanced Ey in longer Lch device due to the alleviation of Kirk effect.
For the 0.18μm DEMOS transistors, according to experimental data and simulation results, hot-carrier-induced ΔNit in the gate overlapped STI region is responsible for the parameter degradation of the device. Moreover, Id(sat) degrades significantly, and is close to Ron degradation. The occurrence of quasi-saturation under high Vg bias is the cause of severe Id(sat) degradation.
Finally, hot-carrier-induced degradation in p-type DEMOS transistors fabricated with 0.35μm is examined. The Vg biased at second Ib peak produces the most device degradation. Hot-carrier-induced ΔNit in channel region leads to VT. ΔNot in the drift region outside poly-gate results in the increase of linear drain current (Idlin) at the beginning of stress, while ΔNit in the drift region under poly-gate causes the turnaround behavior of |Idlin| shift as the stress time is longer.

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[4-1] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose, and T. Roggenbauer, “Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2001, pp. 403-406.
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[5-1] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35µm BCD technology (BCD6),” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2000, pp. 323-326.
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[6-1] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose, and T. Roggenbauer, “Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2001, pp. 403-406.
[6-2] S. Pendharkar, R. Pan, T. Tamura, B. Todd, and T. Efland, “7 to 30V state-of-art power device implementation in 0.25um LBC7 BiCMOS-DMOS process technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2004, pp. 419-422.
[6-3] T. Letavic, R. Cook, R. Brock, H. Effing, and R. Einerhand, “20V asymmetric complementary power device implementation within a 0.25um CMOS technology for power management application,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2005, pp. 159-162.
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[6-7] V. Parthasarathy, V. Khemka, and A. Bose, “SOA improvement by a double RESURF LDMOS technique in a power IC technology,” in IEDM Tech. Dig., 2000, pp. 75-78.
[6-8] M. Annese, P. Montanini, F. Toia, L. Zullino and C. Contiero, “20V-40V symmetrical vertical trench nMOS (SVT MOS) design for display driver ICs,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2006, pp. 53-56.
[6-9] S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang, and C. S. Song, “Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2001, pp. 287-290.

[7-1] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose, and T. Roggenbauer, “Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2001, pp. 403-406.
[7-2] S. Pendharkar, R. Pan, T. Tamura, B. Todd, and T. Efland, “7 to 30V state-of-art power device implementation in 0.25um LBC7 BiCMOS-DMOS process technology,” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2004, pp. 419-422.
[7-3] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35µm BCD technology (BCD6),” in Proceedings of IEEE Int. Symposium Power Semiconductor Devices and IC's, 2000, pp. 323-326.
[7-4] J. F. Chen, K. M. Wu, K. W. Lin, Y. K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proceedings of IEEE Int. Reliability Physics Symposium, 2005, pp. 560-564.
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