隨著電子產品蓬勃發展，電子封裝朝向多功能整合，以往的封裝技術已經無法滿足需求。為了讓有限的封裝體體積提高堆積密度達到高效能與微小化，封裝產業均積極投入研究3D IC堆疊封裝技術的發展。利用進階封裝技術來滿足高階功能晶片市場的需求。而封裝技術朝3D IC堆疊封裝技術發展中，2.5D IC堆疊封裝成為了必要的過渡產品。在2.5D IC堆疊封裝技術中，最重要是矽穿孔(Through Silicon Via, TSV )技術扮演著異質晶片整合的角色，搭配著晶圓級C2W接合技術與覆晶封裝技術，結合多功能元件得以實現。
本文採用ANSYS 15.0 分析2.5D堆疊晶片封裝體結構應力翹曲，並使用陰影疊紋法(Shadow Moiré)量測2.5D堆疊封裝體之熱變形。並利用實驗設計法(Design of Experiment)找出合適的封裝材料，再依據JEDEC規範進行可靠度實驗驗證結果，而可靠度驗證包含溫度循環測試、加速應力測試與高溫儲存測試。透過以上方法來探討封裝材料對2.5D堆疊晶片封裝體結構上翹曲與應力的影響。

In 2.5D IC stacking technology, the most important thing is that the Through Silicon Via (TSV) technology plays the role of heterogeneous wafer integration. It combines wafer-level C2W bonding technology and flip chip packaging technology to realize the integration of multi-function components. In this study, the finite element software ANSYS Workbench 15.0 is used to analyze the stress warping of 2.5D IC package. And the thermal deformation of the 2.5D IC package is measured by the Shadow Moiré method. The DOE (Design of Experiment) method is used to find the appropriate packaging materials, and the reliability test results are verified according to the JEDEC standard. The reliability verification includes MSL pre-condition, 1200 cycles TCT (-40~125℃), 100hrs HAST(130℃/85%RH), and 1000hrs HTS(150℃). Through the above methods, the influence of packaging materials on structural warpage and stress is discussed. After the DOE, used ultra-low CTE substrate can improve package level warpage. The results show that all of packages with ultra-low CTE substrate core and buffered ring adhesive material pass the electrical functional test after reliability test without any crack, delamination, etc.

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