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研究生：	周子翔 Chou, Tzu-Hsiang
論文名稱：	一實現於FPGA的乙太網音訊/視訊處理系統 An Audio/Video Processing System with Gigabit Ethernet: An FPGA Implementation
指導教授：	陳進興 Chen, Chin-Hsing
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	68
中文關鍵詞：	現場可程式化邏輯閘陣列(FPGA) 、乙太網路、音訊處理、視訊處理、影片串流、數位訊號處理、空間音頻
外文關鍵詞：	Ethernet, Audio Processing, Video Processing, Video Streaming, Digital Signal Processing, Spatial Audio
相關次數：	點閱：100 下載：0
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摘 要 I
Abstract II
誌 謝 IV
Acknowledgment V
Contents VI
List of Tables IX
List of Figures X
Chapter 1 Introduction 1
1 Field Programmable Gate Array (FPGA) 1
2 Gigabit Ethernet 2
3 Digital Audio 3
4 Motivation and Contribution 3
5 Thesis Outline 4
Chapter 2 Archeture of the proposed system and its related background knowledge 5
1 Hardware Architecture of the Proposed System 5
1.1 Programming Interface 6
1.2 Cyclone IV E FPGA 7
1.3 Marvell 88E1111 Gigabit Ethernet Transceiver 7
1.4 Wolfson WM8731 Audio Codec 8
2 Physical Layer Specification 8
2.1 Open Systems Interconnection (OSI) Model 8
2.2 Physical Layer 9
2.3 Reduced Gigabit Media Independent Interface (RGMII) 11
3 Network Packet 13
3.1 Packet Format 13
3.2 Ethernet Frame II 13
3.3 IP Packet 15
3.4 UDP Datagram 18
3.5 Discussion 19
4 Audio Signal Processing 20
5 Video Signal Processing 21
Chapter 3 FPGA Implementation of the Proposed System 23
1 Top Level Module of the Proposed System 23
2 The Ethernet Module 25
2.1 Overview of the Ethernet Module 25
2.2 UDP (receiver, transmitter and CRC32)Module 28
2.3 Ethernet FIFO and Payload FIFO 30
3 The Audio Module 31
3.1 Overview of the Audio Module 31
3.2 Controller Module 35
3.3 WM8731 Configuration Module 36
3.4 Digital Audio Processing Module 37
3.5 High Pass Filtering 39
3.6 Low Pass Filtering 41
3.7 Sound Effect 43
Chapter 4 Experimental Results 47
1 Packect Analysis 47
1.1 Devices and Environments 47
1.2 ARP Response Time 47
1.3 Packet Delay Time 48
2 Visualization of Audio Signal 48
3 Experiment Result of the Proposed System 52
Chapter 5 Conclusion and Future Work 59
References 60
Appendix 62
(a) Derivation of the high pass filtering algorithm 62
(b) Derivation of the low pass filtering algorithm 63
(c) Derivation of the sound effect algorithm 65
                                    

[1] T. T. Inc, "DE2-115 User Manual," ed, 2012.
[2] Marvell, "Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Datasheet," ed, 2020.
[3] Wolfson, "WM8731 Product Datasheet v4.9," ed, 2012.
[4] N. Khalilzad, "FPGA implementation of real-time Ethernet communication using RMII interface," ed, 2011.
[5] IEEE, "IEEE Std 802.3ab-1999," ed, 1999.
[6] D. Y. Pan, "Digital Audio Compression," 1993.
[7] S. Shreejith, "VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA," ed, 2017.
[8] Y. Yan, "Design and Implementation of Audio Signal Acquisition System Based on FPGA," ed, 2019.
[9] alexforencich. (2021). verilog-ethernet [Online]. Available: https://github.com/alexforencich/verilog-ethernet.
[10] H. Manjule, "Ethernet Implementation on FPGA," ed, 2020.
[11] S. D. Clifford E. Cummings, Inc., "Simulation and Synthesis Techniques for Asynchronous FIFO Design," ed, 2002.
[12] K. Vaca, "An Open Audio Processing Platform with Zync FPGA," ed, 2019.
[13] Q. Kun, "Design of I2S to AES/EBU Audio Conversion System Based on FPGA," ed, 2019.
[14] G.-M. Sung, "Hardware design on FPGA for Ethernet/SONET bridge in smart sensor system," ed, 2018.
[15] M. Lv, "Design of Audio Signal Analyzer Based on MCU and FPGA," ed, 2020.
[16] L. Stornaiuolo, "FPGA-Based Embedded System Implementation of Audio Signal Alignment," ed, 2019.
[17] W. H. A. Emmanuel S. Kolawole, Penrose Cofie, John Fuller, C. Tolliver, and P. Obiomon, "Design and Implementation of Low-Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA," 2015.

校內：2026-08-20公開
校外：2026-08-20公開電子論文尚未授權公開，紙本請查館藏目錄

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