本論文中，我們主要研究單軸應變技術對奈米尺寸之互補式金氧半場效電晶體及雙載子電晶體特性之影響。藉由四點彎曲技術，我們能夠精準地得到元件特性對不同等級機械應力之反應。
第二章主要介紹壓電效應和四點彎曲技術的理論。此外，試片的準備和四點彎曲裝置也將會在此章節論述。所萃取的互補式金氧半場效電晶體之壓電係數和其它已發表之結果非常接近，因此，利用此彎曲裝置可以在元件上施加均勻而且精準的單軸應變力。
第三章探討將單軸應變技術應用在奈米尺寸之互補式金氧半場效電晶體的擴展性。我們證明出源/汲極串聯電阻以及高的基板摻雜濃度都會大大地降低單軸應變技術在奈米尺寸之互補式金氧半場效電晶體產生的電流提升量。另外，在此章節我們也提出了一個新的方法以萃取製程引起的單軸應變力。
在第四章裡，我們研究單軸應變力對先進65奈米製程之互補式金氧半場效電晶體源/汲極到基板之間的接面漏電流以及閘極漏電流的衝擊。實驗結果顯示出單軸拉伸力可以同時提高N型金氧半場效電晶體的特性並且降低接面漏電流。然而，對於P型金氧半場效電晶體來說，提供單軸壓縮力雖然能提高元件特性，但同時也會增加接面漏電流。在另一方面，提供單軸拉伸和壓縮力可以分別降低N和P型金氧半場效電晶體之閘極漏電流。
第五章裡，我們提出並且研究具有金屬化源/汲極延伸結構之N型高效能應變金氧半場效電晶體，因為其具有低的源/汲極串聯電阻以及較低成本之製程。實驗結果顯示出金屬化源/汲極延伸結構至閘極電極之間的距離會大大影響串聯電阻的大小以及此元件之電特性。藉由最佳化矽化鎳至閘極邊界的距離，此元件將能達到比傳統元件較高的驅動電流、較高的應變力敏感度，同時維持相同的短通道特性、關閉電流以及熱電子可靠度。
第六章裡，我們探討機械單軸應力對矽鍺異質接面雙載子電晶體特性之影響。由於應力引起的載子遷移率及能隙變化，使得集極電流、基極電流、電流增益以及崩潰電壓都會隨著所施加不同應力而有所改變。而提升集極電流及崩潰電壓所須要施加應力的極性是相反的。另外，我們也研究單軸應變力對元件高頻特性之影響。結果顯示200 MPa以下的單軸應變力對最大截止頻率影響有限。
在最後的第七章裡，摘要幾個關鍵結果，並對此論文的未來方向做一建議。

In this dissertation, we investigate the effects of uniaixal strain on the characteristics of nanoscale CMOS and BiCMOS devices. By utilizing a 4-point mechanical bending technique, we explore the accurate strain responses of device characteristics under various levels of mechanical uniaxial stress.
The piezoresitive effects and the theory of the 4-point bending technique are reported in Chapter 2. In addition, the sample preparation and the design of the 4-point bending apparatus are also addressed. Our extracted piezoresistance coefficients of CMOS devices are comparable to that of other published results, and therefore, it is concluded that uniform and precise uniaxial stress can be applied on the devices by the bending apparatus.
The scalability of uniaxial strain technology for nanoscale CMOS devices is investigated in Chapter 3. It is demonstrated that both the source/drain series resistance and high substrate doping would significantly degrade the stain-induced current gain of CMOSFETs in the nanometer regime. Furthermore, a new methodology to evaluate the CESL-induced stress in the transistors is presented by using the 4-point bending technique.
In Chapter 4, we investigate the impact of uniaxial stress on the source/drain-substrate junction leakages and gate leakage currents in state-of-the-art 65nm CMOS transistors. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a trade-off between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied. In the case of gate leakage, application of uniaxial tensile stress to NMOSFET and uniaxial compressive stress to PMOSFET both beneficially reduces the gate leakages.
In Chapter 5, high-performance strained NMOSFETs featuring metallized (NiSi) source/drain extension (M-SDE) are presented and investigated for its low S/D series resistance (RSD) and its cost-effective process. The spacing between metallized extension and gate electrode edge is found to play a very important role in RSD reduction and can significantly affect the electrical characteristics of M-SDE NMOSFETs. A tradeoff between reduced RSD and increased device integrity, such as junction leakage and reliability, is found when the extension-to-gate edge spacing is modulated. By optimizing the NiSi-to-gate edge spacing, M-SDE NMOSFETs exhibit a higher on-current (ION) and higher strain sensitivity while maintaining comparable DIBL, subthreshold swing, IOFF, and hot-carrier reliability as compared to the conventional source/drain extension devices.
Then, in Chapter 6, we study the influences of mechanical uniaxial stress on the characteristics of SiGe heterojunction bipolar transistors (HBTs). Due to the strain-induced modulation of carrier mobility and energy bandgap, the changes in the collector current (IC), base current (IB), current gain (), and breakdown voltage (BVCEO) are related to the strain-polarity. The strain-polarity dependence of the collector current IC is found to be opposite to that of the breakdown voltage BVCEO, revealing a trade-off between uniaxial compressive and tensile stress. The response of the cutoff frequency under uniaxial stress is also investigated. Unlike the obvious changes of DC characteristics, a minor change in the maximum fT could be found for uniaxial stress levels below 200 MPa.
Lastly, in Chapter 7, we summarize key findings and suggest the future works of this study.

Chapter 1
[1.1] S. M. Sze, Physics of Semiconductor Devices. New Jersey: John Wiley & Sons, p.91, 1981.
[1.2] T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahara, T. Tominari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washino, and H. Hosoe, “Integration of a 0.13-mm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance,” in IEDM Tech. Dig., pp. 779–782, 2002.
[1.3] N. Mohta, and S. E. Thompson, “Mobility Enhancement,” IEEE Circuits and Devices Magazine, vol. 21, pp. 18–23, Sep. 2005.
[1.4] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-transport-enhanced channel CMOS for improved power consumption and performance,” IEEE Trans. Electron Devices, vol. 55, pp. 21–39, Jan. 2008.
[1.5] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. Philip Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” in Proc. of the IEEE, vol. 89, pp. 259–288, 2001.
[1.6] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. of the IEEE, vol. 91, pp. 305–327, 2003.
[1.7] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Leong, “Germanium channel MOSFETs: opportunities and challenges,” IBM J. Res. and Dev., vol. 50, pp. 377–386, Jul./Sep. 2006.
[1.8] J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. R. Lin, “Band offset induced threshold variation in strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 24, no. 9, pp. 568–570, Sep. 2003.
[1.9] J. S. Rieh, D. Greenberg, A. Stricker, and G. Freeman, “Scaling of SiGe heterojunction bipolar transistors,” in Proc. of the IEEE, vol. 93, pp. 1522–1538, 2005.
[1.10] International Technology Roadmap for Semiconductors (ITRS), Semiconductor Ind. Assoc., 2005.
[1.11] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs,” in IEDM Tech. Dig., pp. 49–52, 2003.
[1.12] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal oxide semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, pp. 1567–1577, Aug. 1996.
[1.13] W. Zhang, and J. G. Fossum, “On the threshold voltage of strained-Si- Si1-xGex MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 263–268, Feb. 2005.
[1.14] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., pp. 73–76, 2003.
[1.15] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., pp. 221–224, 2004.
[1.16] S. E. Thompson, and et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices , vol. 51, pp. 1790–1797, Nov. 2004.
[1.17] T. Y. Lu, and T. S. Chao, “Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-si gate and capping nitride,” IEEE Electron Device Lett., vol. 26, no. 4, pp. 267–269, Apr. 2005.

Chapter 2
[2.1] J. Richter, Piezo Resistivity in Silicon and Strained Sioicon Germanium. Thesis, Department of Micro and Nanotechnology, Technical University of Denmark, pp. 19–41, 2004.
[2.2] C. S. Smith, “Piezoresistance effect in germanium and silicon,” Physical Review, vol. 94, pp. 42–49, Apr. 1954.
[2.3] J. Richter, O. Hansen, A. N. Larsen, J. L. Hansen, G. F. Eriksen, and E. V. Thomsen, “Piezoresistance of silicon and strained Si0.9Ge0.1,” Sensors and Actuators A, vol. 123–124, pp. 388–396, Apr. 2005.
[2.4] C. H. Cho, R. C. Jaeger, and J. C. Suhling, “The effect of the transverse sensitivity on measurement of the piezoresistive coefficients of silicon,” Jpn. J. of Appl. Phys., vol. 47, pp. 3647–3656, May 2008.
[2.5] S. M. Sze, Semiconductor Sensors. New York: John Wiley & Sons, pp. 160–184, 1994.
[2.6] E. Lund, and T. G. Finstad, “Design and construction of a four-point bending based set-up for measurement of piezoresistance in semiconductors,” Preview of Scientific Instruments, vol. 75, pp. 4960–4966, Nov. 2004.
[2.7] Y. Kanda, “A graphical representation of the piezoresistance coefficients in Silicon,” IEEE Trans. Electron Devices, vol. 29, pp. 64–70, Jan. 1982.
[2.8] C. W. Liu, S. Maikap, and C. Y. Yu, “Mobility-enhancement technologies,” IEEE Circuits and Devices Magazine, pp. 21–36, May 2005.
[2.9] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, pp. 1254–1261, Aug. 2004.
[2.10] V. Moroz, X. Xu, D. Pramanik, F. Nouri, and Z. Krivokapic, “Analyzing strained-silicon options for stress-engineering transistors,” Solid State Technology, pp. 49–51, Jul. 2004.
[2.11] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application,” in Symp. VLSI Tech., pp. 56–57, 2004.
[2.12] L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak, O. Penzin, D. Pramanik, and K. D. Meyer, “Exploring the limits of stress-enhanced hole mobility,” IEEE Electron Device Lett., vol. 26, no. 9, pp. 652–654, Sep. 2005.
[2.13] K. W. Ang, K. J. Chui, H. C. Chin, Y. L. Foo, A. Du, W. Deng, M. F. Li, G. Samudra, N. Balasubramanian, and Y. C. Yeo, “50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: silicon-carbon source/drain regions and tensile stress silicon nitride liner,” in Symp. VLSI Tech., pp. 06–07, 2006.
[2.14] C. H. Ge, and et al., “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., pp. 73–76, 2003.
[2.15] S. E. Thompson, and et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790–1797, Nov. 2004.
[2.16] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors,” IEEE Trans. Electron Devices, vol. 54, pp. 814–821, Apr. 2007.
[2.17] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak, and K. D. Meyer, “Scalability of stress induced by contact-etch-stop layers: a simulation study,” IEEE Trans. Electron Devices, vol. 54, pp. 1446–1453, Jun. 2007.
[2.18] H. Ohta, and et al., “High performance 30 nm gate bulk CMOS for 45 nm node with E-shaped SiGe-SD,” in IEDM Tech. Dig., pp. 129–132, 2005.
[2.19] M. Chu, T. Nishida, X. Lv, N. Mohta, and S. E. Thompson, “Comparison between high-field piezoresistance coefficients of Si metal-oxide-semiconductor field-effect transistors and bulk Si under uniaxial and biaxial stress,” J. Appl. Phys., vol. 103, pp. 113704.1–7, Nov. 2008.
[2.20] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: extending the CMOS roadmap,” IEEE Trans. Electron Devices, vol. 53, pp. 1010–1020, May 2006.
[2.21] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, pp. 1567–1577, Aug. 1996.
[2.22] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 101, pp. 104503–1–22, May 2007.
[2.23] N. Mohta, and S. E. Thompson, “Mobility Enhancement,” IEEE Circuits and Devices Magazine, vol. 21, pp. 18–23, Sep. 2005.
[2.24] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., pp. 129–132, 2005.
[2.25] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si,” in IEDM Tech. Dig., pp. 225–228, 2004.
[2.26] S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for performance enhancement of Si MOSFETs,” in IEDM Tech. Dig., pp. 219–222, 1997.
[2.27] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., pp. 221–224, 2004.
[2.28] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proc. of Int. EDST, pp. 149–152, 2007.
[2.29] J. E. Shigley, C. R. Mischke, and R. G. Budynas, Mechanical engineering design. New York: McGraw Hill, pp. 123–152, 2004.
[2.30] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5 GPa) channel stress,” IEEE Electron Device Lett., vol. 28, no. 9, pp. 58–61, Jan. 2007.
[2.31] K. Uchida, R. Zednik, C. H. Lu, H. Jagannathan, J. McVittie, P. C. McIntyre, and Y. Nishi, “Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs,” in IEDM Tech. Dig., 2004, pp. 229–232.
[2.32] http://www.philtec.com/opDMS-RC.pdf
Chapter3
[3.1] S. E. Thompson et al., “A 90-nm logic technology featuring strained-Silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790–1797, May 2004.
[3.2] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., pp. 73–76, 2003.
[3.3] T. Y. Lu, and T. S. Chao, “Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-si gate and capping nitride,” IEEE Electron Device Lett., vol. 26, no. 4, pp. 267–269, Apr. 2005.
[3.4] K. W. Ang, K. J. Chui, C. H. Tung, N. Balasubramanian, G. S. Samudra, and Y. C. Yeo, “Performance enhancement in uniaxial strained silicon-on-insulator N-MOSFETs featuring silicon-carbon source/drain regions,” IEEE Trans. Electron Devices, vol. 54, pp. 2910–2917, Nov. 2007.
[3.5] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., pp. 129–132, 2005.
[3.6] R. A. Donaton, D. Chidambarrao, J. Johnson, P. Chang, Y. Liu, W. K. Henson, J. Holt, X. Li, J. Li, A. Domenicucci, A. Madan, K. Rim, and C. Wann, “Design and fabrication of MOSFETs with a reverse embedded SiGe (rev. e-SiGe) structure,” in IEDM Tech. Dig., pp. 465–468, 2006.
[3.7] A. T. Bradley, R. C. Jaeger, J. C. Suhling, and K. J. O’Connor, “Piezoresistive characteristics of short-channel MOSFETs on (100) silicon,” IEEE Trans. Electron Devices, vol. 48, pp. 2009–2015, Sep. 2001.
[3.8] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon,” Solid-State Electronics, vol. 48, pp. 561–566, 2004.
[3.9] H. N. Lin, H. W. Chen, C. H. Ko, C. H. Ge, H. C. Lin, T. Y. Huang, and W. C. Lee, “Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs,” IEEE Electron Device Lett., vol. 27, no. 8, pp. 659–661, Aug. 2006.
[3.10] S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, “In search of “forever,” continued transistor scaling one new material at a time,” IEEE Trans. Semi. Manufacturing, vol. 18, pp. 26–36, Feb. 2005.
[3.11] A. Mineji, and S. Shishiguchi, “Ultra shallow junction and super steep halo formation using carbon co-implantation for 65nm high performance CMOS devices,” in IEDM Tech. Dig., pp. 84–87, 2006.
[3.12] J. C. Guo, “Halo and LDD engineering for multiple VTH high performance analog CMOS devices,” IEEE Trans. Electron Devices, vol. 20, pp. 313–322, Aug. 2007.
[3.13] S. I. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec. 1994.
[3.14] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon,” IEEE Trans. Electron Devices, vol. 29, pp. 64–70, Jan. 1982.
[3.15] J. Richter, O. Hansen, A. N. Larsen, J. L. Hansen, G. F. Eriksen, and E. V. Thomsen, “Piezoresistance of silicon and strained Si0.9Ge0.1,” Sensors and Actuators A, pp. 388–396, 2005.
[3.16] J. Richter, Piezo Resistivity in Silicon and Strained Sioicon Germanium. Thesis, Department of Micro and Nanotechnology, Technical University of Denmark, pp. 19–41, 2004.
[3.17] O. N. Tufte, and E. L. Stelzer, “Piezoresistive properties of silicon diffused layers,” J. Appl. Phys., vol. 34, pp. 313–318, Nov. 1963.
[3.18] H. M. Nayfeh, C. W. Leitz, A. J. Pitera, E. A. Fitzgerald J. L. Hoyt, and D. A. Antoniadis, “Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs,” IEEE Electron Device Lett., vol. 24, no. 4, pp. 248–250, Apr. 2003.
[3.19] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, pp. 1254–1261, Aug. 2004.
[3.20] C. Y. Hsieh, and M. J. Chen, “Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs,” IEEE Trans. Electron Devices, vol. 28, pp. 818–820, Sep. 2007.
[3.21] H. S. Yang et al., “Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing,” in Symp. VLSI Tech., pp. 1075–1077, 2004.
[3.22] K. Uejima, H. Nakamura, T. Fukase, S. Mochizuki, S. Sugiyama, and M. Hane, “Highly efficient stress transfer techniques in dual stress liner CMOS integration,” in Symp. VLSI Tech., pp. 220–221, 2007.
[3.23] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5 GPa) channel stress,” IEEE Electron Device Lett., vol. 28, no. 9, pp. 58–61, Jan. 2007.
[3.24] Y. Taur, and T. H. Ning, Fundamentals of Modern VLSI Devices., New York: Cambridge University Press, pp. 20, 1998.
[3.25] S. Wolf, Silicon Processing for the VLSI Era., California: Lattice Press, pp. 235–238, 1995.
[3.26] J. C. Guo, “Halo and LDD engineering for multiple VTH high performance analog CMOS devices,” IEEE Trans. Semiconductor Manufacturing, vol. 20, pp. 313–322, Aug. 2007.
[3.27] J. E. Monaghan, K. L. Lee, M. Ieong, and I. Yang, “Carbon implanted halo for super halo characteristics NFETs in bulk and SOI,” in Proc. of ESSDERC, pp. 155–158, 2001.
[3.28] H. J. Gossmann, C. S. Rafferty, G. Hobler, H. H. Vuong, D. C. Jacobson, and M. Frei, “Suppression of reverse short channel effect by a buried carbon layer,” in IEDM Tech. Dig., pp. 725–728, 1998.
[3.29] S. I. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec. 1994.
[3.30] D. K. Schroder, Semiconductor Material and Device Characterization, New York: John Wiley and Sons Press, pp. 540–550, 1998.
[3.31] C. S. Smith, “Piezoresistance effect in germanium and silicon,” Physical Review, vol. 94, pp. 42–49, Apr. 1954.
[3.32] M. Chu, T. Nishida, X. Lv, N. Mohta, and S. E. Thompson, “Comparison between high-field piezoresistance coefficients of Si metal-oxide-semiconductor field-effect transistors and bulk Si under uniaxial and biaxial stress,” J. Appl. Phys., vol. 103, pp. 113704.1–7, Nov. 2008.
[3.33] M. J. H. van Dal, N. Collaert, G. Doornbos, G. Vellianitis, G. Curatola, B. J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R. G. R. Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R. J. P. Lander, “Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography,” in Symp. VLSI Tech., pp. 110–111, 2007.
[3.34] G. Tsutsui, M. Saitoh, and T. Hiramoto, “Experimental study on superior mobility in (110)-oriented UTB SOI pMOSFETs,” IEEE Electron Device Lett., vol. 26, no. 11, pp. 836–838, Nov. 2005.
[3.35] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak, and K. D. Meyer, “Scalability of stress induced by contact-etch-stop layers: a simulation study,” IEEE Trans. Electron Devices, vol. 54, pp. 1446–1453, Jun. 2007.
[3.36] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors,” IEEE Trans. Electron Devices, vol. 54, pp. 814–821, Apr. 2007.
[3.37] L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak, O. Penzin, D. Pramanik, and K. D. Meyer, “Exploring the limits of stress-enhanced hole mobility,” IEEE Electron Device Lett., vol. 26, no. 9, pp. 652–654, Sep. 2005.

Chapter 4
[4.1] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. of the IEEE, vol. 91, pp. 305–327, 2003.
[4.2] Y. S. Lin, C. C. Wu, C. S. Chang, R. P .Yang, W. M. Chen, J. J Liaw, and C. H. Diaz, “Leakage scaling in deep submicron CMOS for SoC,” IEEE Trans. Electron Devices, vol. 49, pp. 1034–1041, Jun. 2002.
[4.3] S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 363–381, Mar. 2005.
[4.4] H. Luo, H. Yang, and R. Luo, “Accurate and fast estimation of junction band-to-band leakage in nanometer-scale MOSFET,” in APCCAS, pp. 956–959, 2006.
[4.5] S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan, “Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 501–510, Feb. 2004.
[4.6] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. New York: Cambridge University Press, p.94, 1998.
[4.7] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices,” J. Appl. Phys., vol. 91, pp. 258–264, Jan. 2002.
[4.8] S. E. Thompson, P. Packan, and M. Bohr, “MOS scaling: transistor challenges for the 21st century,” Intel Tech. Journal, pp. 1–19, 1998.
[4.9] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., pp. 73–76, 2003.
[4.10] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process -induced strained-Si: extending the CMOS roadmap,” IEEE Trans. Electron Devices, vol. 53, pp. 1010–1020, May, 2006.
[4.11] J. P. Han, H. Utomo, L. W. Teo, N. Rovedo, Z. Luo, R. Krishnasamy, R. Stierstorfer, Y. F. Chong, S. Fange, H. Ng, J. Holt, T. N. Adam, J. Kempisty, A. Gutmann, D. Schepis, S. Mishra, H. Zhuang, J. J. Kim, J. Li, R. Murphy, R. Davis, B. S. Lawerence, A. Madan, A. Turansky, L. Burns, R. Loesing, S. D. Kim, R. Lindsay, G. Ghiulli, R. Amos, M. Hierlemann, D. Shum, J. J. Ku, J. Sudijono, M. Ieong, “Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices,” in IEDM Tech. Dig., pp. 59–62, 2006.
[4.12] J. J. Wortman, J. R. Hauser, and R. M. Burger, “Effect of mechanical stress on p-n junction device characteristic,” J. Appl. Phys., vol. 35, pp.2122–2131, Jul. 1964.
[4.13] P. Smeys, P. B. Griffin, Z. U. Rek, I. D. Wolf, and K. C. Saraswat, “Influence of process-induced stress on device characteristics and its impact on scaled device performance,” IEEE Trans. Electron Devices, vol. 46, pp. 1245–1252, Jun. 1999.
[4.14] A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers, and K. Maex, “Silicide and shallow trench isolation line width dependent stress induced junction leakage,” in Symp. VLSI Tech., pp. 180–181, 2000.
[4.15] P. Smeys, P. B. Griffin, and K. C. Saraswat, “Influence of post-oxidation cooling rate on residual stress and pn-junction leakage current in LOCOS isolated structures,” IEEE Trans. Electron Devices, vol. 43, pp. 1989–1993, Jun. 1996.
[4.16] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, Jun. 2005.
[4.17] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proc. of EDST, pp. 149–152, 2007.
[4.18] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, pp. 052108–1–3, Jan. 2006.
[4.19] C. Y. Hsieh, and M. J. Chen, “Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs,” IEEE Trans. Electron Devices, vol. 28, pp. 818–820, Sep. 2007.
[4.20] M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D’Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, “High performance CMOS fabricated on hybrid substrate with different crystal orientations,” in IEDM Tech. Dig., pp. 453–458, 2003.
[4.21] S. Okamoto, K. Miyashita, N. Yasutake, T. Okada, H. Itokawa, I. Mizushima, A. Azuma, H. Yoshimura, and T. Nakayama, “Study on high performance (110) PFETs with embedded SiGe,” in IEDM Tech. Dig., pp. 277–280, 2007.
[4.22] T. Y. Liow, K. M. Tan, R. T. P. Lee, C. H. Tung, G. S. Samudra, N. Balasubramanian, and Y. C. Yeo, “N-channel (110)-sidewall strained FinFETs with silicon-carbon source and drain stressors and tensile capping layer,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 1014–1016, Nov. 2007.
[4.23] T. Irisawa, T. Numata, T. Tezuka, K. Usuda, N. Sugiyama, and S. I. Takagi, “Device design and electron transport properties of uniaxially strained-SOI tri-gate nMOSFETs,” IEEE Trans. Electron Devices, vol. 55, pp. 649–654, Feb. 2008.
[4.24] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, J. Shah, N. Zelick, and R. Chau, “Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering,” in Symp. VLSI Tech., pp. 50–51, 2006.
[4.25] H. S. Momose, T. Ohguro, K. Kojima, S. I. Nakamura, and Y. Toyoshima, “1.5-nm gate oxide CMOS on (110) surface-oriented Si substrate,” IEEE Trans. Electron Devices, vol. 50, pp. 1001–1008, Apr. 2003.
[4.26] A. Teramoto, T. Hamada, M. Yamamoto, P. Gaubert, H. Akahori, K. Nii, M. Hirayama, K. Arima, K. Endo, S. Sugawa, and T. Ohmi, “Very high carrier mobility for high-performance CMOS on a Si (110) surface,” IEEE Trans. Electron Devices, vol. 54, pp. 1438–1445, Jun. 2007.
[4.27] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, “A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films,” in IEDM Tech. Dig., pp. 213–216, 2004.
[4.28] Z. Luo, Y. F. Chong, J. Kim, N. Rovedo, B. Greene, S. Panda, T. Sato, J. Holt, D. Chidambarrao, J. Li, R. Davis, A. Madan, A. Turansky, O. Gluschenkov, R. Lindsay, A. Ajmera, J. Lee, S. Mishra, R. Amos, D. Schepis, H. Ng, and K. Rim, “Design of high performance PFETs with strained Si channel and laser anneal,” in IEDM Tech. Dig., pp. 489–492, 2005.
[4.29] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon,” Solid-State Electronics, vol. 48, pp. 561–566, 2004.
[4.30] M. J. Chen, H. T. Huang, C. S. Hou, and K. N. Yang, “Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET’s,” IEEE Electron Device Lett., vol. 10, no. 4, pp. 134–136, Apr. 1998.
[4.31] S. Severi, B. J. Pawlak, R. Duffy, E. Augendre, K. Henson, R. Lindsay, and K. D. Meyer, “Arsenic junction thermal stability and high-dose boron-pocket activation during SPERin nMOS transistors,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 198–200, Mar. 2007.
[4.32] S. M. Sze, Physics of Semiconductor Devices. New Jersey: John Wiley & Sons, p.91, 1981.
[4.33] A. Czerwinski, E. Simoen, A. Poyai, and C. Claeys, “Activation energy analysis as a tool for extraction and investigation of p-n junction leakage current components,” J. Appl. Phys., vol. 94, pp.1218–1221, July. 2003.
[4.34] Y. S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto, M. Miyajima, S. Satoh, and T. Sugii, “Suppression of defect formation and their impact on short channel effects and drivability of pMOSFET with SiGe source/drain,” in IEDM Tech. Dig., pp. 871–874, 2006.
[4.35] T. J. Wang, H. W. Chen, P. C. Yeh, C. H. Ko, S. J. Chang, J. Yeh, S. L. Wu, C. Y. Lee, W. C. Lee, and D. D. Tang, “Effects of mechanical uniaxial stress on SiGe HBT characteristics,” J. Electrochem. Soc., vol. 154, pp. H105–H108, Jun. 2007.
[4.36] J. F. Creemer, and P. J. French, “The Orientation dependence of the piezojunction effect in bipolar transistors,” in Proc. of the 30th European Solid-State Device Research Conference, pp. 416–419, 2000.
[4.37] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5GPa) channel stress,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 58–61, Aug. 2007.
[4.38] Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, “Polarity dependent gate tunneling currents in dual-gate CMOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 2355–2360, Nov. 1998.
[4.39] Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 540–542, Nov. 2000.
[4.40] W. C. Lee, and C. Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Trans. Electron Devices, vol. 48, pp. 1366–1373, Jul. 2001.
[4.41] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices,” J. Appl. Phys., vol. 91, pp. 258–264, Jan. 2002.
[4.42] K. Alam, S. Zaman, M. M. Chowdhury, M. R. Khan, and A. Haque, “Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors,” J. Appl. Phys., vol. 92, pp. 937–943, Jul. 2002.
[4.43] Y. S. Choi, J. S. Lim, T. Numata, T. Nishida, and S. E. Thompson, “Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation poteneials for germanium,” J. Appl. Phys., vol. 102, pp. 104507–1–5, Nov. 2007.
[4.44] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal oxide semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, pp. 1567–1577, Aug. 1996.
[4.45] J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, “Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress,” Appl. Phys. Lett., vol. 89, pp. 073509–1–3, Aug. 2006.
[4.46] M. Saitoh, S. Kobayashi, and K. Uchida, “Physical understanding of fundamental properties of Si (110) pMOSFETs inversion-layer capacitance, mobility universality, and uniaxial stress effects,” in IEDM Tech. Dig., pp. 711–714, 2007.
[4.47] M. Saitoh, A. Kaneko, K. Okano, T. Kinoshita, S. Inaba, Y. Toyoshima, and K. Uchida, “Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction,” in Symp. VLSI Tech., pp. 18–19, 2008.
[4.48] K. Uchida, A. Kinoshita, and M. Saitoh, “Carrier transport in (110) nMOSFETs: subband structures, non-parabolicity, mobility characteristics, and uniaxial stress engineering,” in IEDM Tech. Dig., pp. 1019–1021, 2006.

Chapter 5
[5.1] J. M. Larson, and J. P. Snyder, “Overview and status of metal S/D schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, pp. 1048–10582, May 2006.
[5.2] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, “Enhancement of hot-electron generation rate in schottky source metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 76, no. 26, pp. 3392–3394, Jun. 2000.
[5.3] J. P. Snyder, C. R. Helms, and Y. Nishi, “Analysis of the potential distribution in the channel region of a platinum silicided source/drain metal oxide semiconductor field effect transistor,” Appl. Phys. Lett., vol. 74, no. 22, pp. 3407–3409, May 1999.
[5.4] M. Zhang, J. Knoch, J. Appenzeller, and S. Mantl, “Improved carrier injection in ultrathin-body SOI schottky-barrier MOSFETs,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 223–225, Mar. 2007.
[5.5] C. H. Ko, H. W. Chen, T. J. Wang, T. M. Kuan, J. W. Hsu, C. Y. Huang, C. H. Ge, L. S. Lai, and W. C. Lee, “NiSi schottky barrier process-strained Si (SB-PSS) CMOS technology for high performance applications,” in Symp. VLSI Tech., pp. 80–81, 2006.
[5.6] S. Zhu, J. Chen, M. F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type schottky barrier source/drain MOSFET using Ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004.
[5.7] M. Jang, Y. Kim, J. Shin, and S. Lee, “Characterization of Erbium-silicided Schottky diode junction,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 354–356, Jun. 2005.
[5.8] G. P. Lousberg, H. Y. Yu, B. Froment, E. Augendre, A. De Keersgieter, A. Lauwers, M. F. Li, P. Absil, M. Jurczak, and S. Biesemans, “Schottky-barrier height lowering by and increase of the substrate doping in PtSi Schottky barrier source/drain FETs,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 123–125, Feb. 2007.
[5.9] M. Zhang, J. Knoch, Q. T. Zhao, St. Lenk, U. Breuer, and S. Mantl, “Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs,” in Proc. of ESSDERC, pp. 457–460, 2005.
[5.10] Z. Zhang, Z. Qiu, R. Liu, M. Ostling, and S. Zhang, “Schottky-barrier height tuning by means of Ion implantation into preformed silicide films followed by drive-in anneal,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 565–568, July 2007.
[5.11] T. Kinoshita, R. Hasumi, M. Hamaguchi, K. Miyashita, T. Komoda, A. Kinoshita, J. Koga, K. Adachi, Y. Toyoshima, T. Nakayama, S. Yamada, and F. Matsuoka, “Ultra low voltage operations in bulk CMOS logic circuits with dopant segregated schottky source/drain transistors,” in IEDM Tech. Dig., pp. 71–74, 2006.
[5.12] J. Knoch, M. Zhang, Q. T. Zhao, St. Lenk, S. Mantl, and J. Appenzeller, “Effective schottky barrier lowering in silicon-on-insulator schottky-barrier metal-oxide- semiconductor field-effect transistors using dopant segregation,” Appl. Phys. Lett., vol. 87, no. 26, pp. 263505 1–3, Dec. 2005.
[5.13] H. W. Chen, C. H. Ko, T. J. Wang, C. H. Ge, K. Wu, and W. C. Lee, “Enhanced Performance of strained CMOSFETs using metallized source/drain extension (M-SDE),” in Symp. VLSI Tech., pp. 118–119, 2007.
[5.14] S. Kim, S. Narasimha, and K. Rim, “An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs,” in IEDM Tech. Dig., pp. 155–158, 2005.
[5.15] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, pp. 1254–1261, Aug. 2004.
[5.16] S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, “In search of “forever,” continued transistor scaling one new material at a time,” IEEE Trans. Semi. Manufacturing, vol. 18, pp. 26–36, Feb. 2005.
[5.17] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5GPa) channel stress,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 58–61, Aug. 2007.
[5.18] H. N. Lin, H. W. Chen, C. H. Ko, C. H. Ge, H. C. Lin, T. Y. Huang, and W. C. Lee, “Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs,” IEEE Electron Device Lett., vol. 27, no. 8, pp. 659–661, Aug. 2006.
[5.19] S. I. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec. 1994.
[5.20] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of short-channel schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate,” Jpn. J. Appl. Phys., vol. 38, pp. 6226–6231, Nov. 1999.
[5.21] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K, Uchida, and J. Koga, “Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,” in Symp. VLSI Tech., pp. 168–169, 2004.
[5.22] J. Seger, P. E. Hellstrom, J. Lu, B. G. Malm, M. von Haartman, M. Ostling, and S. L. Zhang, “Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator,” Appl. Phys. Lett., vol. 86, no. 25, pp. 253507 1–3, Jun. 2005.
[5.23] T. Yamaguchi, K. Kashihara, T. Okudaira, T. Tsutsumi, K. Maekawa, T. Kosugi, N. Murata, J. Tsuchimoto, K. Shiga, K. Asai, and M. Yoneda, “Suppression of anomalous gate edge leakage current by control of Ni silicidation region using Si ion implantation technique,” in IEDM Tech. Dig., pp. 855–858, 2006.
[5.24] F. Deng, K. Ring, Z. F. Guan, S. S. Lau, W. B. Dubbelday, N. Wang, and K. K. Fung, “Structural investigation of self-aligned silicidation on separation by implantation oxygen,” J. Appl. Phys., vol. 81, no. 12, pp. 8040–8046, Jun. 1997.
[5.25] S. Wolf, Silicon processing for the VLSI era, volume 3: The submicron MOSFET. Sunset Beach: Lattice Press, p.592, 1995.

Chapter6
[6.1] T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahara, T. Tominari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washino, and H. Hosoe, “Integration of a 0.13-m CMOS and a high performance self-aligned SiGe HBT featuring low base resistance,” in IEDM Tech. Dig., pp. 779–782, 2002.
[6.2] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., pp. 73–76, 2003.
[6.3] S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, “In search of “forever,” continued transistor scaling one new material at a time,” IEEE Trans. Semi. Manufacturing, vol. 18, pp. 26–36, Feb. 2005.
[6.4] S. E. Thompson, and et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790–1797, Nov. 2004.
[6.5] J. S. Dunn, and et al., “Foundation of RF CMOS and SiGe BiCMOS technologies,” IBM J. Res. and Dev., vol. 47, pp. 101–138, Mar. 2003.
[6.6] F. Yuan, S. R. Jan, S. Maikap, Y. H. Liu, C. S. Liang and C. W. Liu, “Mechanically strained Si-SiGe HBTs,” IEEE Electron Device Lett., vol. 25, no. 7, pp. 483–485, Jul. 2004.
[6.7] B. M. Haugerud, M. B. Nayeem, R. Krithivasan, Y. Lu, C. Zhu, J. D. Cressler, R. E. Belford, and A. J. Joseph, “The effects of mechanical planar biaxial strain in Si/SiGe HBT BiCMOS technology,” Solid-State Electronics, vol. 49, no. 6, pp. 986–990, Jun. 2005.
[6.8] J. F. Creemer and P. J French, “The orientation dependence of the piezojunction effect in bipolar transistors,” in Proc. of ESSDERC, pp. 416–419, 2000.
[6.9] J. F. Creemer, F. Fruett, G. C. M. Meijer, and P. J French, “The piezojunction effect in silicon sensors and circuits and its relation to piezoresistance,” IEEE Sensors Journal., vol. 51, pp. 98–108, Aug. 2001.
[6.10] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon,” Solid-State Electronics, vol. 48, pp. 561–566, 2004.
[6.11] Y. Taur, and T. H. Ning, Fundamentals of Modern VLSI Devices., New York: Cambridge University Press, pp. 356–368, 1998.
[6.12] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, Jun. 2005.
[6.13] F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf and T. Skotnicki, “Low temperature characterization of effective mobility in uniaxially and biaxially strained N-MOSFETs,” in Proc. of ESSDERC, pp. 525–528, 2005.
[6.14] B. M. Haugerud, L. A. Bosworth and R. E. Belford, “Mechanically induced strain enhancement of metal-oxide-semiconductor field effect transistors,” J. Appl. Phys., vol. 94, pp. 4102–4107, Sep. 2003.
[6.15] L. Fang, W. L. Wang, P. D. Ding, K. J. Liao and J. Wang, “Study on the piezoresistive effect of crystalline and polycrystalline diamond under uniaxial,” J. Appl. Phys., vol. 86, pp. 5185–5193, Nov. 1999.
[6.16] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon,” IEEE Trans. Electron Devices, vol. 29, pp. 64–70, Jan. 1982.
[6.17] S. M. Sze and G. Gibbons, Appl. Phys. Lett., vol. 8, pp. 111–113, 1966.
[6.18] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., pp. 129–132, 2005.
[6.19] M. W. Hsieh, C. C. Ho, H. P. Wang, C. Y. Lee, G. J. Chen, D. T. Tang and Y. J. Chan, “Frequency response improvement of 120 GHz fT SiGe HBT by optimizing the contact configurations,” IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, pp. 967–970, 2004.
[6.20] J. F. Creemer and P. J French, “A new model of the effect of mechanical stress on the saturation current of bipolar transistors,” Sens. Actuator A, , vol. 97–98, pp. 289–295, 2002.