| 研究生: |
胡肇峻 Hu, Chao-Chun |
|---|---|
| 論文名稱: |
錐形矽穿孔應力特性之研究 A Study of the Stress Characteristics of Tapered TSVs |
| 指導教授: |
周榮華
Chou, Jung-Hua |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 工程科學系 Department of Engineering Science |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 中文 |
| 論文頁數: | 51 |
| 中文關鍵詞: | 錐形TSV 、熱應力 |
| 外文關鍵詞: | Tapered TSV, Thermal stress, Simulation |
| 相關次數: | 點閱:86 下載:9 |
| 分享至: |
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在三維集成中,矽通孔(Through Silicon Via,TSV)是實現垂直互連的一種重要結構。然而該技術仍面臨許多挑戰性的問題,如何迅速準確建立其等效模型、提取熱應力分佈便是其中之一。常用的分析方法是將TSV 等效成圓柱,應用傳輸線理論分析。然而,受限於製程技術,製造的矽通孔傾角最高可達20 度,此時傳統傳輸線方法將不再適用,對錐形TSV 的建模分析就顯得十分必要。
本文針對錐型 TSV,通過Ansys模擬研究它從室溫溫度25 度升至275 度時由於材料間熱膨脹係數不匹配產生的熱應力情況。本文的主要工作歸納如下:掌握了應用於三維互連的TSV 結構及其熱應力的產生原理,基於以上內容選擇單層單一TSV及陣列TSV模型進行研究。建立模型,施加熱負載,對其進行熱應力分析,在相同上半徑下,圓柱TSV 相較於錐形TSV的最大熱應力數值更大,分佈更不均勻的特點。且錐形TSV相較於圓柱TSV有較小的熱應力影響範圍。
In three-dimensional IC integration, Through Silicon Via (TSV) is an important structure for vertical interconnection. However, this technology still faces many challenging problems such as how to quickly and accurately establish its equivalent model and extract the thermal stress distribution. A commonly used model is to convert TSV equivalently into a cylinder and apply transmission line theory analysis. However, limited by the process technology, the tilt angle of the manufactured TSV can be up to 20 degrees. At this time, the traditional transmission line method is still applicable, and modeling and analysis of the tapered TSV are necessary.
In this thesis, for the tapered TSV, finite element simulation is used to study the thermal stress caused by the mismatch of thermal expansion coefficients between materials at room temperature from 25 °C to 275 °C. The main work of this thesis is summarized as follows: The TSV structure applied to three-dimensional interconnects and the principle of thermal stress generation are mastered. Based on the above content, a single-layer single TSV and array TSV models are selected for research. The model is established, the thermal load is applied, and the thermal stress is analyzed. Under the same upper radius, the cylindrical TSV has a larger maximum thermal stress than the tapered TSV, and the distribution is more uneven. And the tapered TSV has a smaller thermal stress range than the cylindrical TSV.
[1] J. Lu, "3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems," in Proceedings of the IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
[2] F. P. Carson, Y. C. Kim and I. S. Yoon, "3-D Stacked Package Technology and Trends," in Proceedings of the IEEE, vol. 97, no. 1, pp. 31-42, Jan. 2009.
[3] J. U. Knickerbocker et al., "Three-dimensional silicon integration," in IBM Journal of Research and Development, vol. 52, no. 6, pp. 553-569, Nov. 2008.
[4] X. Zhang et al., "Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 4, pp. 510-518, April 2011.
[5] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps," in IEEE Transactions on Advanced Packaging, vol. 32, no. 4, pp. 720-728, Nov. 2009.
[6] L. Jiang, Y. Liu, L. Duan, Y. Xie, and Q. Xu. "Modeling TSV open defects in 3Dstacked DRAM." Paper presented at the Test Conference (ITC), 2010 IEEE International (2010).
[7] S. E. Thompson, Guangyu Sun, Youn Sung Choi and T. Nishida, "Uniaxial-process-induced strained-Si: extending the CMOS roadmap," in IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
[8] A. P. Karmarkar, X. Xu and V. Moroz, "Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)," 2009 IEEE International Reliability Physics Symposium, Montreal, QC, 2009, pp. 682-687.
[9] P. Dixit, S. Yaofeng, J. Miao, J. H. Pang, R. Chatterjee, and R. R. Tummala. "Numerical and experimental investigation of thermomechanical deformation in high-aspect-ratio electroplated through-silicon vias." Journal of the 71 Electrochemical Society, 155 (12), H981-H986 (2008).
[10] N. Ranganathan, K. Prasad, N. Balasubramanian, and K. Pey. "A study of thermomechanical stress and its impact on through-silicon vias." Journal of micromechanics and microengineering, 18 (7), 075018 (2008).
[11] K. H. Lu, Xuefeng Zhang, S. Ryu, J. Im, Rui Huang and P. S. Ho, "Thermo-mechanical reliability of 3-D ICs containing through silicon vias," 2009 59th Electronic Components and Technology Conference, San Diego, CA, 2009, pp. 630-634.
[12] L. J. Ladani. "Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits." Microelectronic Engineering, 87 (2), 208-215 (2010).
[13] K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim. "Stressdriven 3D-IC placement with TSV keep-out zone and regularity study." Paper presented at the Proceedings of the International Conference on Computer-Aided Design (2010).
[14] J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan. " TSV stress aware timing analysis with applications to 3D-IC layout optimization. " Paper presented at the Proceedings of the 47th Design Automation Conference (2010).
[15] W. Kwon, K. Teo, S. Gao, T. Ueda, T. Ishigaki, K. Kang, and W. Yoo. "Stress evolution in surrounding silicon of Cu-filled through-silicon via undergoing thermal annealing by multiwavelength micro-Raman spectroscopy." Applied Physics Letters, 98 (23), 232106 (2011).
[16] S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P. S. Ho, and R. Huang. "Impact of nearsurface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects." IEEE Transactions on Device and Materials Reliability, 11 (1), 35- 43 (2011).
[17] X. Gao, R. Chen, C. Li, and S. Liu. "Dimension optimization of through silicon via (TSV) through simulation and design of experiment (DOE)." Paper presented at the Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on (2012).
[18] A. Heryanto, W. Putra, A. Trigg, S. Gao, W. Kwon, F. Che, X. Ang, J. Wei, R. I Made, and C. L. Gan. "Effect of copper TSV annealing on via protrusion for TSV wafer fabrication." Journal of Electronic Materials, 1-10 (2012).
[19] S.-K. Ryu, K.-H. Lu, T. Jiang, J.-H. Im, R. Huang, and P. S. Ho. "Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3- D integration. " IEEE Transactions on Device and Materials Reliability, 12 (2), 255- 262 (2012).
[20] S.-K. Ryu, Q. Zhao, M. Hecker, H.-Y. Son, K.-Y. Byun, J. Im, P. S. Ho, and R. Huang. "Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects." Journal of Applied Physics, 111 (6), 063513 (2012).
[21] C. Lee, T. Yang, C. Wu, K. Kao, C. Fang, C. Zhan, J. Lau, and T. Chen. "Impact of high density TSVs on the assembly of 3D-ICs packaging." Microelectronic Engineering, 107, 101-106 (2013).
[22] J. Zhang, L. Zhang, Y. Dong, H. Li, C. M. Tan, G. Xia, and C. S. Tan. "The dependency of TSV keep-out zone (KOZ) on Si crystal direction and liner material." Paper presented at the 3D Systems Integration Conference (3DIC), 2013 IEEE International (2013).
[23] Y. Zhu, J. Zhang, H. Y. Li, C. S. Tan, and G. Xia. "Study of near-surface stresses in silicon around through-silicon vias at elevated temperatures by Raman spectroscopy and simulations." IEEE Transactions on Device and Materials Reliability, 15 (2), 142-148 (2015).
[24] H.-Y. Tsai and C.-W. Kuo. "Thermal stress and failure location analysis for through silicon via in 3D integration." Journal of Mechanics, 32 (01), 47-53 (2016).
[25] X. Gagnard and T. Mourier. "Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration." Microelectronic Engineering, 87(3), 470-476 (2010).
[26] C. Laviron, B. Dunne, V. Lapras, P. Galbiati, D. Henry, F. Toia, S. Moreau, R. Anciant, C. Brunet-Manquat, and N. Sillon. "Via first approach optimisation for through silicon via applications." Paper presented at the Electronic Components and Technology Conference, 2009. ECTC 2009. 59th (2009).
[27] A.Redolfi, D. Velenis, S. Thangaraju, P. Nolmans, P. Jaenen, M. Kostermans, U. Baier, E. Van Besien, H. Dekkers, and T. Witters. "Implementation of an industry compliant, 5× 50μm, via-middle TSV technology on 300mm wafers." Paper presented at the Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st (2011).
[28] B.Majeed, D. S. Tezcan, B. Vandevelde, F. Duval, P. Soussan, and E. Beyne. "Electrical characterization, modeling and reliability analysis of a via last TSV." Paper presented at the Electronics Packaging Technology Conference (EPTC), 2010 12th (2010).
[29] T. Pandhumsoporn, L. Wang, M. Feldbaum, P. Gadgil, M. Puech, and P. Maquin. "High-etch-rate deep anisotropic plasma etching of silicon for MEMS fabrication." Paper presented at the 5th Annual International Symposium on Smart Structures and Materials (1998).
[30] L. Hofmann, R. Ecke, S. E. Schulz, and T. Gessner. "Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives." Microelectronic Engineering, 88(5), 705-708 (2011).
[31] H. Ling, H. Cao, Y. Guo, H. Yu, M. Li, and D. Mao. "Influence of leveler concentration on copper electrodeposition for through silicon via filling." Paper presented at the Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP'09. International Conference on (2009).
[32] W. H. Teh, D. Marx, D. Grant, and R. Dudley. "Backside infrared interferometric patterned wafer thickness sensing for through-silicon-via (TSV) etch metrology." IEEE transactions on semiconductor manufacturing, 23 (3), 419-422 (2010).
[33] M. Motoyoshi. "Through-silicon via (TSV)." Proceedings of the IEEE, 97 (1), 43- 48 (2009).
[34] R. E. Hummel. "Electronic properties of materials: Springer Science & Business Media." (2011).
[35] R. C. Jaeger, J. C. Suhling, and A. A. Anderson. "A [100] silicon stress test chip with optimized piezoresistive sensor rosettes." Paper presented at the Electronic Components and Technology Conference, 1994. Proceedings, 44th (1994).
[36] J.-Y. Yan, S.-R. Jan, Y.-C. Huang, H.-S. Lan, C. Liu, Y.-H. Huang, B. Hung, K.-T. Chan, M. Huang, and M.-T. Yang. "Compact modeling and simulation of TSV with experimental verification." Paper presented at the VLSI Technology, Systems and Application (VLSI-TSA), 2016 International Symposium on (2016).
[37] F. P. Incropera, A. S. Lavine, T. L. Bergman, and D. P. DeWitt. "Fundamentals of heat and mass transfer: Wiley." (2007).
[38] H.-H. Lee. "Taguchi methods: principles and practices of quality design, " Gau Lih Book Co. Ltd., Taiwan (2000).
[39] H.-H. Lee. "Finite element simulations with ANSYS workbench 16," SDC publications (2015).
[40] J. Wortman and R. Evans. "Young's modulus, shear modulus, and Poisson's ratio in silicon and germanium." Journal of Applied Physics, 36 (1), 153-156 (1965).