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研究生： 楊顗民
Yang, Yi-Ming
論文名稱： 高效能及低功率之可變延遲進位預測加法器設計
High-Performance Low-Power Carry Speculative Addition with Variable Latency
指導教授： 林英超
Lin, Ing-Chao
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 47
中文關鍵詞： 傳統加法器 、近似加法器 、預測加法器 、錯誤偵測 、錯誤修正 、可變延遲
外文關鍵詞： Traditional adder, Approximate adder, Speculative adder, Error detection, Error recovery, Variable latency
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    • 在許多的應用中，加法器是最關鍵的算術單元之一。而算術電路的整體效能也都取決於加法器的運算能力。因此，可以藉由提升加法器的效能來減少電路的執行時間。然而，傳統的n位元加法器為了提供100%準確的結果，在時間延遲上會有一個下限Ω(logn)的限制，使得加法器的效能無法顯著的被提升。因此，為了可以有效的提升傳統加法器的效能，已經有許多的近似加法器被提出來。這些近似加法器是藉由犧牲運算的準確度讓電路可以有更少的延遲時間及功率消耗。
    在此篇論文中，我們提出一個高效能及低功率的進位預測加法器(CSPA)。這種加法器和另一篇研究所提出來的預測加法器相比之下，可以減少更多的延遲時間及功率消耗。另外，為了提供正確的結果，我們也加入了錯誤偵測及錯誤修正的電路來建構一個以CSPA為基礎的可變延遲加法器(VLCSPA)，讓錯誤的結果可以被修正。從實驗結果得知，相較於先前研究所提出的預測進位選擇加法器，我們提出的CSPA最多有26.59%的效能提升，降低14.06%的使用面積，以及減少19.03%的功率消耗。 而且VLCSPA的平均延遲時間是近似於CSPA的延遲時間。

    Adders are one of the most critical arithmetic functional units in many applications. The overall performance of these arithmetic circuits depends on the throughput of the adder. Therefore, the execution time can be reduced by improving the performance of adder. In order to provide 100% accurate results, the traditional adders have the delay lower bound Ω(logn). Thus, the performance of those adders cannot be improved significantly. To effectively improve the performance of the traditional adder, many approximate adders have been proposed. These approximate adders decrease the circuit delay and power consumption by sacrificing the computing accuracy. In this paper, we propose a high-performance and low-power carry speculative adder (CSPA) which can reduce the delay and power consumption compared with another speculative adder. In addition, to provide correct results, we also propose an error detection and recovery circuit constructing a CSPA-based variable latency addition (VLCSPA) to recover the results when an error occurs. The experimental results show our proposed CSPA has up to 26.59% performance improvement, 14.06% area reduction and 19.03% power saving compared with the speculative carry-select adder that was proposed in previous research work. Further, the average latency of the VLCSPA is close to that of the CSPA.

    中文摘要 i Abstract ii 誌謝 iii Contents iv List of Tables vi List of Figures vii Chapter 1 Introduction 1 1.1 Background 1 1.2 Our Contributions 4 1.3 Paper Organization 5 Chapter 2 Preliminaries 6 2.1 Variable Latency Design 6 2.2 Speculative adders 8 2.3 Metric for Approximate Design 12 Chapter 3 METHODOLOGY 13 3.1 Carry Speculative Adder (CSPA) 13 3.2 Error rate analysis 17 3.3 Critical path delay analysis of CSPA 21 3.4 Error Detection and Recovery 22 3.5 Variable Latency Carry Speculative Adder 25 Chapter 4 Experimental Setup and Results 27 4.1 Error rate and accuracy analysis when different input width used in the predictor circuit 28 4.2 Area comparisons 31 4.3 Power consumption comparisons 34 4.4 Critical path delay and average latency comparisons 36 4.5 Error-Energy-Delay product model 39 Chapter 5 Conclusion 44 References 45

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