本論文主要針對24-GHz微波CMOS射頻前端RFICs及毫米波電路之研究設計，晶片製作使用國家晶片中心提供的標準TSMC CMOS 0.18 μm以及TSMC RF CMOS 0.13 μm製程，內容分為兩個部份：第一部分介紹毫米波汽車防撞雷達與毫米波的研究背景，第二部份為毫米波CMOS RFICs之設計與量測。
首先介紹K頻帶汽車防撞雷達射頻前端收發機系統規劃，針對包括靈敏度、SNR、解析度、等進行討論，並針對所規劃高解析汽車防撞雷達進行鏈路預算，希望對射頻系統規劃者與電路設計者有參考作用。毫米波CMOS RFICs設計方面，24-GHz單端輸入差動輸出(single-in differential-out, SIDO) CMOS低雜訊放大器採用trifilar變壓器提供良好的平衡器特性、級間匹配以及簡化偏壓電路設計等好處。量測結果在24-GHz有14 dB的差動增益、雜訊指數為4.3 dB、1-dB增益壓縮點輸入功率為-10.7 dBm以及0.6 dB與0.47°的增益誤差與相位誤差，整體消耗功率為20.2 mW。混頻器採用雙閘極架構之雙平衡式雙閘極混頻器，在限定功率消耗的考量下選擇電晶體尺寸達成低功率設計，並且對電晶體之Cgs、Cgd、Gm、Rds及NFmin等小訊號參數對於不同偏壓變化情形決定偏壓點的。電路佈局之傳輸走線均使用Sonnet考量金屬的寄生與電磁耦合效應，由Agilent ADS進行共同模擬，務必要求佈局與模擬一致。量測結果在RF端於24 GHz的輸入返回損耗部分為12 dB，LO端於24 GHz的輸入返回損耗部分為16dB，以及IF端輸出主動平衡器的輸入返回損耗量測結果為12 dB。

This thesis presents the research on 24-GHz CMOS RFICs and millimeter-wave circuit design for short-range vehicular collision-avoidance radar application. The RFICs are fabricated with TSMC 0.18 μm 1P6M standard and TSMC RF CMOS 0.13μm process. Agilent ADS is used to integrate the co-simulation design. A 24-GHz single-in differential-out (SIDO) CMOS low-noise amplifier (LNA) integrated a trifilar transformer is designed. The trifilar transformer in the SIDO LNA can achieve a good balanced characteristics, inter-stage matching and reduction of the bias-circuits. The designed 24-GHz double-balance dual-gate CMOS mixer uses a multi-bias technique to enhance the linearity.

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