本論文旨在探討65 nm嵌入式非揮發性記憶體低產品良率的成因與其相關改善技術之研究。本論文主著重於實驗觀察到的現象及趨勢，找出影響良率的主要因素，並透過分析及實驗，提升產品良率，達到能夠穩定量產的水準。
嵌入式非揮發性記憶體在未來的數位產品應用的重要性與日俱增，尤其是互聯網、移動裝置中，都必須要有一定容量的非揮發性記憶體用來儲存所需的基本資料，爾後才能透過網路連線將資料傳送到目的地加以分析。隨著製程的微縮及複雜化，嵌入式非揮發性記憶體已較純邏輯產品增加許多道特殊製程。一般而言，嵌入式快閃記憶體技術需在標準邏輯製程上外加11～12層光罩，如何決定這些額外產生的特殊製程順序及衍生出的問題加以分析並解決，是一極重要課題。
本論文研究工作，主要透過低良率產品的失效分析，找出原因並調變製程參數，以提升良率。經過不斷的電性分析以及分批實驗結果，抽絲剝繭解決隱藏於製程中的所有問題，最終將良率提升到量產的要求。
根據製程中良率提升的實驗結果及過程，我們發現當製程微縮時，任何額外的製程容易影響元件的特性，有些是製程產生的缺陷，使元件短路，有些是因為額外製程中的熱預算使原先的元件特性漂移，造成低良率。於製程開發過程中，發現透過額外的碳離子植入可以抑制多晶矽結晶成長，減少磷離子透過結晶介面擴散，雖然實驗結果發現跟植入的能量及劑量無關，但還是決定將此步驟加在製程中，以增加製程穩定性；光阻與多晶矽間在黃光曝光顯影前，透過乾蝕刻產生薄氧化層可以減少光阻在顯影後殘留的程度，進而改善蝕刻缺陷的產生，可以使缺陷數目從上千顆的不穩定狀態大幅降低到不到100顆的穩定狀態；額外植入硼離子可以讓靜態隨機存取記憶體(SRAM)的元件分布特性更加收斂，使其最低操作電壓從原本的1080 mV縮小到850 mV，這將使SRAM能在高頻(100 Mhz)下操作而不會有tail bit速度跟不上而導致的良率損失。在此當時，新型材料與結構的非揮發性記憶體，如FeRAM、RRAM、MRAM的開發也在如火如荼的進行中，但目前這些新型非揮發性記憶體的可靠度仍然需要時間去證明。相較之下，微縮傳統架構嵌入式非揮發性記憶體，仍然是值得投資的項目，藉由此次在65 nm平台中的經驗，相信能夠縮短在下個製程微縮平台的開發時間。

The present study aims at the process development and improvement for 65 nm embedded flash yieldenhancement. Methods used to improve yield includes: (a) introducing an extra oxygen treatment on POLY surface to reduce photo resister residue post photography development, (b) using SRAM single device characteristicsmeasurement by nano-probing to find out failsure root cause, (c) using split PB space and extra P+_POLY imp to suppress N type POLY dosage diffusion to PMOS gate and higherPMOS Vth issue, and (d) using carbon implant to reduce POLY grain. Final process qualification is passed criteria with 10 years.

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