互補式金氧半影像感測元件（CMOS Image Sensor，CIS）在過去幾年來，已被廣泛地應用在生活周遭的許多機器設備之中。由於CIS能操作在較低的工作電壓並消耗較少的功率，加上能以互補式金氧半（CMOS）邏輯製程製造，進而提供單晶片系統（System On a Chip，SOC），CIS已漸漸取代傳統的電荷耦合元件（Charge Coupled Device，CCD），並開始應用於數位攝影機、光學滑鼠及行動電話等消費性電子產品中。然而，利用CMOS邏輯製程卻使CIS產生許多效能上的缺失：較高的元件驅動電流將同時提高CIS的暗態漏電流（Dark Current），並引發白畫素（White Pixel）的產生；較厚的後段金屬內連線則會提高元件的光互擾雜訊（Optical Crosstalk）；而堆疊使用二氧化矽（SiO2）、氮氧化矽（SiON）及氮化矽（SiN）等介電材料則可能導致元件感光度的退化。在另一方面，由於強大的市場需求，元件的尺寸必須不斷地縮小，使得產品在降低體積的同時，必須能保有相同、甚至更高的解析度，但在元件縮小化的過程當中，面臨了許多元件效能上的挑戰，其中兩項重要的問題為：一、較小的有效受光面積（Fill Factor，FF）將大幅降低元件的感光能力，二、較小的畫素面積則將嚴重地提高元件的互擾雜訊（Crosstalk）。因此，本論文深入研究在元件縮小化的過程中，所面臨在電性及光學上挑戰，並提出數種有效的方法來改進元件的特性。

　　首先，吾人提出採用較薄的磊晶晶片（Epitaxial Wafer，Epi Wafer），來降低元件的電互擾雜訊（Electrical Crosstalk），特別是針對在長波長的響應下。實驗結果顯示，經過適當的設計，採用更薄的磊晶晶片，能使畫素在縮小後，依舊保有與大畫素相同的電互擾雜訊。

　　第二，吾人建議在縮小畫素尺寸過程中，同時降低後段金屬層及介電層的厚度，來減輕元件的光互擾雜訊（Optical Crosstalk）。為了適用CMOS邏輯製程來生產，CIS必須面臨使用較厚的金屬層及介電層，但這也導致了嚴重的光互擾雜訊，因此，隨著畫素的縮小，元件後段高度的縮減已成為必然的趨勢。

　　第三，吾人成功開發出三種先進的結構，包含光導結構（Light Guide，LG）、空氣護環結構（Air-Gap-Guard-Ring，AGGR）以及空氣護環一體成形微透鏡結構（Air-Gap-in-situ-MicroLens，AGML），藉由光線全反射的原理，來大幅降低CIS的光互擾雜訊。實驗結果證實，搭配較低的元件後段高度，空氣護環一體成形微透鏡結構能最有效地降低光互擾雜訊並同時提高元件的感光能力，使得元件在縮小後，仍具有、甚至超越大尺寸元件的光學性能。

　　第四，吾人提出藉由移除吸光二極體（Photodiode）上部份的淺溝隔絕結構（Shallow Trench Isolation，STI），並沉積氮氧化矽，來改進元件的量子效率（Quantum Efficiency，QE）。實驗結果顯示，利用吾人所提出的方法，可有效地提高吸光二極體的量子效率，特別是對藍色入射光的響應。另一方面，也必須同時適當地調整介電層的厚度及其他參數，來提高元件的感光能力。

　　最後，吾人提出一個有效的方法，來評估CIS因為熱載子（Hot Carriers）可能產生的性能退化，進而提供設計者一個準則去避免因熱載子而產生的特性退化。

　　Solid-state image sensors, such as the CMOS image sensor (CIS) and the charge-coupled device (CCD), have been applied widely in various machines. In the past several years, a great deal of attention have been paid to the CIS for its superior advantages over CCD in areas such as lower voltage and lower power consumption, compatible with the standard CMOS logic process, and especially providing the integration solution for the SOC. Simultaneously, the CIS has been considered as a viable alternative to the CCD in many applications, such as the digital still camera, the optical mouse and the mobile phone. However, several disadvantages of the logic compatible CIS were found, for example, higher device driving current caused the higher dark signal and the white pixel, thicker backend thickness enlarged optical crosstalk and the degraded photosensitivity from using multi-dielectric films, including SiON, SiO2 and SiN. On the other hand, the pixel size is shrunk continuously for the strong demand of the higher resolution and smaller chip size. But accompany the shrinking of pixel size, several challenges were found. Two major of them are the sensitivity degradation caused by the less fill factor, and the pixel crosstalk enhancement induced by the smaller geometry. In this thesis, we propose some effective approaches to improve the pixel performance of the deep sub-micron CIS.

　　Firstly, we propose to use the thinner epitaxial (Epi) wafer to reduce the electrical crosstalk, especially for longer wavelength light. Because the light with different wavelengths generates the photoelectron at different depth in a Si substrate i.e., the longer wavelength, the deeper penetration depth is. Therefore, adopting the thinner Epi wafer can reduce the electrical crosstalk. With proper process design, the electrical crosstalk of a smaller pixel size can be good enough as the previous larger pixel size.

　　Secondly, we suggest using the thinner backend (TB) scheme to reduce the optical crosstalk as shrinking the pixel size. In order to be compatible with the CMOS logic technology, large inter-metal thickness for lower capacitance is adopted in the CIS process. However, if we scale the device horizontal dimension without thinning the vertical thickness, the optical crosstalk would be enhanced due to the oblique incident light would easily illuminate on the nearby pixel. Hence, thinning down the backend thickness is necessary while shrinking the pixel size. Furthermore, thinning down the backend thickness not only reduces the crosstalk but also suppresses the sensitivity degradation as increase of incident light angles.

　　Thirdly, we develop three advanced backend structures, i.e., Light Guide (LG), Air-Gap-Guard-Ring (AGGR) and Air-Gap-in-situ-MicroLens (AGML), to reduce the optical of the CIS. As continually shrinking the sensor pixel size and adopting multi-layer metal in deep sub-micron process, the crosstalk issue and sensitivity degradation are getting worse for the severe optical scattering. To find out more power solutions for improving the optical performance of the CIS becomes necessary. Based on the Snall’s law, using the refractive index (RI) difference between different dielectric films and the air make the light total reflection occur in the backend of the CIS, thus effectively suppressing the optical crosstalk. Consequently, by using the TB+AGML structure, the pixel size can be further downscaled to smaller geometry with good optical performance.

　　Fourthly, a novel dielectric structure by removing the shallow trench isolation (STI) from the photodiode area and then forming a deposition of SiON was proposed to improve the CIS sensitivity. In the advanced CIS technology, both silicide and borderless contact (BLC) processes have been adopted, thus the photodiode must be placed below the STI SiO2, with SiON film on its surface, in order to enhance the sensitivity. However, as the incident light passes through the dielectric film with abrupt changes of (refractive index) RI, such as low RI (1.46) / high RI (2.15) / low RI (1.46) / high RI (3.44) for ILD_SiO2 / SiON / STI_SiO2 / Si, a destructive interference occurs between these interfaces, thus degrading the sensitivity of the CIS. By using the proposed structure, experimental results show better quantum efficiency (QE) compared to conventional structure, especially illuminated at the blue light. Therefore, we show that the photodiode under Si surface would provide better spectral response than the photodiode under the STI. On the other hand, QE of the photodiode with different dielectric film thickness is simulated. We find that the SiON film is another key layer that might degrade the QE of the photodiode. Consequently, proper choice of the dielectric film structure and the thickness can result in higher quantum efficiency for CMOS image sensors.

　　Finally, we proposed an effective method to evaluate the degradation, thus a guideline has been provided for designers to prevent the performance degradation of CIS from hot carriers effect. For the active pixel sensor (APS) operated at some special conditions, hot carriers generated at the source follower (SF) transistor have been found to degrade the pixel performance such as the increase of dark signal and the decrease of operation range. We study the degradation mechanism of the pixel output signal induced by hot carriers with overall useful bias conditions. And based on the studies, an effective method was proposed to evaluate the degradation. Thus, a guideline has been provided for designers to prevent the performance degradation of APS from hot carriers.

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