隨著各式可攜式產品的不同功能需求增加，更多的功能被整合在一個面積受限的系統單晶片中，新一代的可攜式產品所消耗的能耗大幅增加且不容忽視，並導致供電電池的使用時間提前縮短，其中靜態隨機存取記憶體在系統晶片中佔據了極高的功耗比例，因此若是能儘量降低靜態隨機存取記憶體的能耗，渴望能使整體系統晶片受惠。
本篇論文提出一個採用字組線交錯控制機制、分割位元線和區域感測放大器等技術的改良架構，可降低存取功耗以及加速存取時間，進而達到較低能耗的目標，且僅使用單一電源以顧慮應用於可攜式產品時的系統層級成本考量。
上述所提出的設計以台積電九十奈米互補式金氧半導體製程技術，實現一個四千字元大小的近臨界電壓靜態隨機存取記憶體，從模擬結果顯示，這個具有改良架構的靜態隨機存取記憶體，可正確的操作在供應電壓為三百毫伏，能耗僅零點一三二微微焦耳，相較於傳統靜態隨機存取記憶體平均可節省55%的能耗及提升約1.91倍的操作速度。

With the increasing demands for versatile portable products, more and more functions are integrated into an area-constrained system. The energy consumed by the new-generation portable product increases dramatically and leads to short battery lifetime. Since the energy consumption of Static Random Access Memory (SRAM) occupies higher ratio than other components in systemona-chip(SoC), the overall system energy consumption can be lowered by reducing the energy consumption of SRAM.We propose a modified SRAM architecture that adopts wordline interleaving controller, hierarchical bit-lines and local sense amplifier methods to save energy consumption and to reduce access time. Besides, this work also maintains only one supply voltage as a power source to the SRAM for keeping the cost of portable products down under system level consideration. A 4Kb near-threshold SRAM macro with proposed techniques was implemented by using TSMC 90nm CMOS technology. According to the simulation results, the proposed SRAM can correctly operate at 0.3V supply voltage and only consume around 0.1323pJ. Compared to the traditional 6T SRAM, our proposed SRAM has an average 55% energy saving and around 1.91 times access speed improvement.

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