| 研究生: |
吳承翰 Wu, Cheng-Han |
|---|---|
| 論文名稱: |
應用於射頻收發機系統之寬頻再生式除頻器、可調式衰減器與超低功耗倍頻器之研製 Broadband Frequency Dividers, Variable Attenuator, and Ultra-Low-Power Frequency Multiplier for RF Transceiver System Applications |
| 指導教授: |
王永和
Wang, Yeong-Her |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 中文 |
| 論文頁數: | 120 |
| 中文關鍵詞: | 收發機 、再生式除頻器 、CML 、鎖相迴路 、可調式衰減器 、倍頻器 |
| 外文關鍵詞: | transceiver, regenerative divider, current-mode-logic, phase-locked loop, variable attenuator, multiplier |
| 相關次數: | 點閱:115 下載:8 |
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本論文主要研究應用於Ku至Ka頻段 (12-40GHz) 之射頻收發機電路元件,首先使用TSMC 90nm CMOS製程研製一個具有除四及正交相位輸出的再生式除頻器,本次設計是使用了次諧波混頻器、中央抽頭變壓器及源極注入CML除二電路,形成一再生式除頻器架構。由變壓器設計的源極注入CML電路,可改善傳統差動注入CML的高頻雜散電容效應,提高注入功率與操作頻寬,提升再生式除頻器的鎖頻範圍,不須再使用級間buffer,節省除頻器功耗與面積。量測後的鎖頻範圍為20.1-24.8GHz,核心電路的消耗功率為13.7mW,晶片面積為0.69 × 0.85 mm2。
第二部分為使用正交注入式CML的除三再生式除頻器與除五再生式除頻器的研製。其架構為使用兩組Gilbert Mixer與帶通濾波器並結合正交注入式的CML電路,來實現兩顆具有高除數、寬鎖頻範圍以及正交輸入正交輸出功能的再生式除頻器。與傳統差動注入式CML比較,運用正交注入式CML電路,能有效改善再生式除頻器的鎖頻範圍,並應用於正交鎖相迴路。關於除三與除五的除頻器量測結果顯示,核心電路消耗功率分別為10.73mW/ 14.8mW,且擁有12.5-23GHz (59%) / 7.2-19GHz (90%)的超寬鎖頻範圍及高達52.3/ 133.5的FOM值。
第三部分為一個新的相位抵消式可調式衰減器,架構上使用了Lange Coupler、反射型相移器(RTPS)以及Wilkinson Power Combiner,使用相位合成抵消的方式來作功率的衰減,研製一可調式衰減器。本次設計架構並非直接使用主被動元件來衰減功率,能夠降低元件的高頻寄生效應,改善操作頻率以及頻寬,並能有低的功率損失和寬廣的衰減範圍。此電路量測的操作頻寬為30-40GHz,可調的衰減量為4.5-23.7dB之間,範圍約為19.2dB,在操作頻寬下的反射損失皆大於10dB。
第四部分為提出新式諧波增強技術的超低功耗五倍頻器。架構為使用一組交叉耦合電晶體對與次諧波混頻器作疊接而成,此次創新概念使用交叉耦合對來提供迴路增益可有效增強高次諧波功率,解決高倍數倍頻器因高次諧波訊號功率過小而難以實現的問題,此外架構上同時使用電流共用技術以降低核心電路功耗。經由模擬,本次設計的倍頻器具有五倍的高倍數、23-27.5GHz的操作頻寬、大於20dB的諧波抑制能力、以及低達0.18mW的超低功耗。
The main research of this thesis is for the application of RF receiver circuit in Ku-Ka band. First, a divide-by-4 regenerative frequency divider (RFD) with quadrature outputs is implemented in TSMC 90 nm CMOS process. The structure which uses feedback to combine sub-harmonic mixer, center-tap transformer, and source-injection current-mode-logic (CML) circuit becomes a regenerative divider. The source-injection CML circuit can improve the parasitic effects of the conventional differential CML circuit which operate in high frequency to increase the injection power of the CML and to operate in high frequency. Therefore, the design has wide locking range and need no inter-stage buffer, so it can save power consumption and chip area. The core circuit consumes 13.7mW, the locking range is 20.1-24.8 GHz, and the chip size is 0.69 x 0.85 mm2.
The second part of this thesis presents a divide-by-3 and a divide-by-5 regenerative frequency divider which use quadrature-injection CML to implement by TSMC 90 nm CMOS process. The architecture consists of two Gilbert mixers, two bandpass filters, and quadrature-injection CML to realize two frequency divider with high division number, wide locking range, and the function of quadrature inputs and outputs. Compared with traditional differential-injection CML, the locking range of quadrature-injection CML is improved extensively. Furthermore, the proposed divider can use in quadrature phase-locked loop. The power consumption of the measured divide-by-3 divider and the measured divide-by-5 divider is 10.73mW and 14.8mW, the locking range is 12.5-23GHz (59%) and 7.2-19GHz (90%), and the FOM is up to 52.3 and 133.5.
The third part used 0.25-μm GaN pHEMT process to demonstrate a fixed-phase variable attenuator with novel phase-cancellation technique. The circuit with phase-cancellation technique constitutes by Lange coupler, reflective type phase shifter, and Wilkinson power combiner to control power level and achieve a variable attenuator. The new structure avoided signal power passing through the dissipative devices, so it can reduce the parasitic effects of the devices. Therefore, it has low power loss, wide operation range, and good attenuation range. The measured bandwidth is 30-40 GHz, the attenuation range is about 19.2dB from 4.5-23.7dB, and the return loss at operation bandwidth is larger than 10 dB.
The fourth part proposed an ultra-low-power quintupler with novel harmonic-enhanced technique by TSMC 90 nm CMOS process. The circuit combines a sub-harmonic mixer and a cross-coupled pair transistor to generate a five times frequency signal. The new idea is that by using the cross-coupled pair transistor to provide circuit loop gain can enhance the high-order harmonic power and solves the high-order harmonic power is too small to realize high multiply number. In addition, the circuit also uses current-reuse technique to reduce power consumption. By simulation, this quintupler has as five times as high multiply number, the operation range is 23-27.5GHz , the harmonic suppression is larger than 20 dB, and the power is low down to 0.18mW.
Chapter 1
[1] B. Razavi,“RF IC design challenges,”Design Automation Conference, 1998.Proceedings, 15-19 June 1988.
Chapter 2
[1] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[2] D. M. Pozar, Microwave and RF design of wireless systems, New York :JohnWiley, 2001.
[3] S. A. Mass, Microwave Mixers, 2nd ed. Boston, MA: Artech House.
[4] M. T. Faber, J. Chramiec, and M. E. Adamski, Microwave and Millimeter-Wave Diode Frequency Multipliers. Boston, MA: Artech House, 1995.
[5] S. A. Maas, Nonlinear Microwave and RF circuits 2nd ed., Artech House, 2003.
[6] S. A. Maas, The RF and Microwave Circuit Design Cookbook, Artech House,1998.
Chapter 3
[1] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004.
[2] T. N. Luo, S. Y. Bai, and Y. J. E. Chen, “A 60-GHz 0.13-μm CMOS divide-by-three frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2409-2415, Nov. 2008.
[3] T. N. Luo and Y. J. E. Chen, “A 44-GHz 0.18-μm CMOS super-harmonic frequency divider,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1409-1412.
[4] C. Kromer, G. V. Buren, G. Sialm, T. Morf, F. Ellinger, and H. Jzckel, “A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 10, pp. 564-566, Oct. 2006.
[5] H. Zheng and H. C. Luong, “Ultra-low-voltage 20-GHz frequency dividers using transformer feedback in 0.18-μm CMOS process, ” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2293-2302, Oct. 2008.
[6] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda, “20-GHz quadrature injection-locked LC dividers with enhanced locking range,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 610-618, Mar. 2008.
[7] Y. T. Chen, M. W. Li, H. C. Kuo, T. H. Huang, and H. R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector, ” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 60-67, Jan. 2012.
[8] C. C. Chen, C. H. Wang, B. J. Huang, H. W. Tsao, and H. Wang, “A 24-GHz divide-by-4 injection-locked frequency divider in 0.13-μm CMOS technology,” in IEEE Proc. Asia-Pacific Microw. Conf., pp. 340-343, Nov. 2007.
[9] M. W. Li, P. C. Wang, T. H. Huang, and H. R. Chuang, “Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency dividers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 679-685, Mar. 2012.
[10] H. Zheng and H. Luong, “A double-balanced quadrature-input quadrature-output regenerative frequency divider for UWB synthesizer applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, pp.2944, 2008.
[11] A. Mirzaei, M. Heidari, R. Bagheri, and A. Abidi, “Multi-phase injection widens lock range of ring-oscillator-based frequency dividers,” IEEE J. Solid-State Circuits, vol. 43, pp.656, 2008.
[12] S. L. Jang and C. W. Chang "A 90 nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range," IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 229-231, Apr. 2010.
[13] Y. S. Chen, C. W. Chang and C. C. Liu "A wide-locking range ÷3 injection-locked frequency divider using linear mixer," IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 390-392, Jul. 2010.
[14] S. H. Lee, “A low voltage divide-by-4 injection-locked frequency divider with quadrature output,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 373-375, May 2007.
[15] Z. D. Huang, C. Y. Wu, and B. C. Huang, “Design of 24-GHz 0.8-V 1.51-mW coupling current-mode injection-locked frequency divider with wide locking range, ” IEEE Trans. Microw. Theory Tech., vol. 57, no. 8, Aug. 2009.
[16] Y. H. Kuo, J. H. Tsai, H. Y. Chang, T. W. Huang, “Design and Analysis of a 77.3% Locking-Range Divide-by-4 Frequency Divider”, in IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, Oct. 2011.
[17] P. K. Tsai, T. H. Huang and Y. H. Pang, “CMOS 40 GHz divide-by-5 injection-locked frequency divider, ” Electron. Lett., vol. 46, no. 14, Jul. 2010.
[18] J. R. Long, “Monolithic Transformers for Silicon RF IC Design”, in IEEE J. Solid-State Circuits, vol. 35, no. 9, Sep. 2000.
[19] J. C. Chien and L. H. Lu, “Analysis and design of wideband injection-locked ring oscillators with multiple-input injection,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1906-1915, Sep. 2007.
[20] Y. S. Lin, C. L. Lu, and Y. H. Wang, “A 24-GHz triple-mode programmable frequency divider in 0.13-μm CMOS technology,” in IEEE Proc. Asia-Pacific Microw. Conf., pp. 381-384, 2009.
Chapter 4
[1] Y. Y. Huang, W. Woo, C. H. Lee, and J. Laskar, “A CMOS wide-bandwidth high-power linear-in-dB variable attenuator using body voltage distribution method,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 303-306, 2010.
[2] C. E. Saavedra, and B. R. Jackson, “Voltage-variable attenuator MMIC using phase cancellation,” IEE Proceedings-Circuits, Devices and Systems, vol. 153, no.5 , pp.442-446, Oct. 2006.
[3] C. W. Wang, H. S. Wu, M. J. Chiang, and C. K. C. Tzuang, “A 24 GHz CMOS miniaturized phase-invertible variable attenuator incorporating edge-coupled synthetic transmission lines,” IEEE Microwave Symposium Digest, 2009. MTT'09. IEEE MTT-S International. 2009. pp. 841-844.
[4] K. Sun, M. Choi, and D. Weide, “A PIN diode controlled variable attenuator using a 0-dB branch-line coupler,” IEEE Microwave and Wireless Component Letters, vol. 15, no. 6, pp. 440-442, Jun. 2005.
[5] C. E. Saavedra, and Y. Zheng, “Ring-hybrid microwave voltage-variable attenuator using HFET transistors,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 7, Jun. 2005.
[6] F. Ellinger, R. Vogt, and W. Bachtold, “Compact reflective-type phase shifter MMIC for C-band using a lumped-element coupler,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 5, pp. 913-917, May 2001.
[7] K. Miyaguchi, M. Hieda, K. Nakahara, H. Kurusu, M. Nii, M. Kasahara, T. Takagi, and S. Urasaki, “An ultra-broad-band reflection-type phase shifter MMIC with series and parallel LC circuits,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp.2446-2452, Dec. 2001.
[8] C. S. Lin, S. F. Chang, C. C. Chang and Y. H. Shu, “Design of a reflection-type phase shifter with wide relative phase shift and constant insertion loss,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 9, pp.1862, Sep. 2007.
[9] H. Kwon, H. Lim and B. Kang, “Design of 6–18 GHz wideband phase shifters using radial stubs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp.205, Mar. 2007.
[10] L. Sjogren, D. Ingram, M. Biedenbender, R. Lai, B. Allen, and K. Hubbard, “A low phase-error 44-GHz HEMT attenuator,” IEEE Microwave and Guided Wave Letters, vol. 8, No. 5, May 1998.
[11] S. M. Daoud and P. N. Shastry, “A novel wideband MMIC voltage controlled attenuator with a bandpass filter topology,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp.2576-2583, Jun. 2006.
[12] B. Min and G. M. Rebeiz, “A 10-50-GHz CMOS distributed step attenuator with low loss and low phase imbalance,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp.2547, Nov. 2007.
[13] C. R. Trent and T. M. Weller, “S-band reflection type variable attenuator,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 7, pp.243 -245, Jul. 2002.
Chapter 5
[1] P. K. Tsai, and T. H. Huang, “Integration of current-reused VCO and frequency tripler for 24-GHz low-power phase-locked loop applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 4, pp. 199–203, Apr. 2012.
[2] C. N. Kuo, H. S. Chen, and T. C. Yan, “A K-band CMOS quadrature frequency tripler using sub-harmonic mixer,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 12, pp.822-824, Dec. 2009.
[3] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “Injection-locked CMOS frequency doublers for u-Wave and mm-Wave applications,” IEEE Journal of Solid-State Circuits, vol. 45, no.8, pp.1565, Aug. 2010.
[4] K. Y. Lin, J. Y. Huang, and S. C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 5, pp. 308-310, Mar. 2009.
[5] J. H. Chen, and H. Wang, “A high gain, high power K-band frequency doubler in 0.18 um CMOS process,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 9, pp.522-524, Sep. 2010.
[6] M. C. Chen, and C. Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869-1878, Aug. 2008.
[7] Y. T. Lo, and J. F. Kiang, “A 0.18 um CMOS self-mixing frequency tripler,” IEEE Microw. Wirel. Compon. Lett., vol. 22, no. 2, pp. 79-81, Feb. 2012.
[8] B. R. Jackson, F. Mazzilli, and C. E. Saavedra, “A frequency tripler using a subharmonic mixer and fundamental cancellation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp.1083-1090, May. 2009.
[9] N. C. Kuo, J. C. Kao, Z. M. Tsai, K. Y. Lin, and H. Wang, “A 60-GHz frequency tripler with gain and dynamic-range enhancement,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp.660-671, Mar. 2011.
[10] P. K. Tsai, C. Y. Liu, and T. H. Huang, “A CMOS voltage controlled oscillator and frequency tripler for 22-27GHz local oscillator generation,” IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 9, pp.492-494, Sep. 2011.
[11] W. L. Chan, J. R. Long, and J. J. Pekarik, “A 56-to-65GHz injection-locked frequency tripler with quadrature outputs in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 480-629, Feb. 2008.
[12] C. N. Kuo, and T. C. Yan, “A 60 GHz injection-locked frequency tripler with spur suppression,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 10, pp.560-562, Oct. 2010.
[13] Y. Zheng, and C. E. Saavedra, “A broadband CMOS frequency tripler using a third-harmonic enhanced technique,” IEEE Journal of Solid-State Circuits, vol. 42, no.40, pp.2197-2203, Oct. 2007.