有鑑於矽鍺合金與作為閘極材料的二氧化矽在半導體產業的大量應用，本論文旨在以電性量測的方式，探討矽鍺薄膜以及其氧化物之界面特性。
本實驗所使用的樣品為矽鍺合金基板，使用原子力顯微鏡以局部場致氧化的方式在矽鍺薄膜上製作矩形的氧化物，並放置於掃描電子顯微鏡腔體中，以兩根鎢針在矽鍺薄膜表面以及其氧化層上在不同定點做電流—電壓量測，根據鎢針接觸面的不同，我們能將電路分成三種類型，分別為SiGe-SiGe (SS)、Oxide-Oxide (OO)與SiGe-Oxide (SO)等三種迴路。從SS電路中我們能得到Metal-Semiconductor (MS)接面的量測，而OO電路能獲得的則是Metal-Insulator-Semiconductor (MIS)接面，SO電路則同時能得到MS與MIS接面的資訊，從三種電路的電性量測中，透過擬合分析的方式能夠解析出蕭特基能障以及穿隧能障的量值，並從其中探討當氧化物在MS接面界面處形成時，蕭特基能障與穿隧能障的變化，並推測出鍺原子的析出與其不平均積聚的現象，因此獲得場致氧化後界面狀態以及結構的變化，同時與穿透式電子顯微鏡之cross section結果做應證。

Using the scanning probe assisted anodic oxidation, we could locally fabricate patterned SiO2 layer on SiGe thin film with nanometer size. To investigate the electron transport properties of the patterned SiO2 layer on SiGe, we used two tungsten tips assembled in nanomanipulators of SEM system to probe various SiO2 patterns on SiGe substrate. Based on the electrical transportation results, the contact interfaces of tungsten tip/SiGe and tungsten tip/ SiO2 reveal large differences, which is consistent with the cross-sectional TEM images. The I-V measurements also show the interfacial states and structures of oxide layer, which is essential properties of gate dielectric layer when it comes to the applications of SiGe related devices such as CMOS, HBTs.

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