在本論文中，提出數個射頻接收機前端電路中的低雜訊放大器之設計，包含以下電路：可切換式電感之多模式低雜訊放大器、可切換式堆疊電感之多模式低雜訊放大器、可切換電感與電容之多模式低雜訊放大器、可切換式電感與頻率補償之雙模式低雜訊放大器。另外，針對無線收發機前段做系統整合之應用，並且延續實驗室學長之研究，設計以高功率元件模組應用於LTE通訊頻段之功率放大器。
晶片一、可切換式電感之多模式低雜訊放大器，最重要的特色在於，其利用開關切換電感，使整體電路具有三種操作模式。分別操作於模式一、單頻 (5.2 GHz)，模式二、雙頻 (2.3/5.8 GHz)，模式三、雙頻 (2.4/5.2 GHz) 三個不同的模式。其操作於模式一時，當頻率為5.15 GHz，量測的增益為10.4 dB，雜訊指數為6.69 dB。其操作於模式二時，當頻率為1.9/5.75 GHz，量測到的增益為10.5/10.3 dB，雜訊指數為6.6/6.9 dB。其操作於模式三時，當頻率為1.9/4.8 GHz，量測到的增益為11.3/11.3 dB，雜訊指數為6.0/6.6 dB。
晶片二、可切換式堆疊電感之多模式低雜訊放大器，為了改善傳統利用電感當作切換頻段的架構，所造成晶片面積過大的缺點，於是將兩個用於切換之電感做垂直式地堆疊，縮小晶片面積。其操作模式一為單頻 (5.5 GHz)，量測到的增益為13 dB，雜訊指數為6 dB。模式二為雙頻 (2.2/5.5 GHz)，量測到增益為4.7/11 dB，雜訊指數為7.6/5.7 dB。模式三為雙頻 (2.1/5.7 GHz)，量測到的增益為3.3/11.5 dB，雜訊指數為6.9/5.9 dB。
晶片三、可切換電感與電容之多模式低雜訊放大器，則是針對晶片一架構作延伸與改良，於切換式電感的三個電感中，將不被開關控制的電感並聯一切換電容，使之除了原本能應用於WiFi/WiMAX通訊系統之外，還增加可應用之LTE通訊系統。當其操作模式一為雙頻 (2.0/4.9 GHz)，量測到的增益為7.4/11 dB，雜訊指數為7.5/6.1 dB。其操作模式二為雙頻 (2.3/5.4 GHz)，量測到的增益為8.1/9.2 dB，雜訊指數為6.9/6.6 dB。其操作模式三為雙頻 (1.9/5.3 GHz)，量測到的增益為11.3/9.7 dB，雜訊指數為6.2/6.5 dB。其操作模式四為單頻 (1.8 GHz)，量測到的增益為11.4 dB，雜訊指數為6.4 dB。
晶片四、可切換式電感與頻率補償之雙模式低雜訊放大器，此晶片為創新之架構，其特色在於能明顯地切換操作頻段，並且同時具有單頻與雙頻的模式，幾乎涵蓋WiMAX的所有頻段。其操作於單頻模式下，諧振頻率為3.5 GHz，模擬的增益為11.2 dB，雜訊指數為3.8 dB。當其操做於雙頻模式下，諧振頻率為2.4 GHz與5.2 GHz，模擬的增益為16.8/16.4 dB，雜訊指數為3.3/3.5 dB。
晶片五、六為以高功率元件模組設計可應用於LTE通訊頻段之功率放大器，晶片五為分析高功率元件應用於射頻功率放大器上的可靠度影響，並且測試其實際應用於電路中，最大的飽和輸出功率極限。其操作頻率為2.6 GHz，量測結果如下，S11為-16 dB，S22為-6 dB，S21為-1.1 dB，S12為-29 dB，其沒有增益的主要原因為電源饋入電流過大，導致電源饋入之金屬走線燒毀，對電路特性造成破壞。
晶片六，則是針對晶片五的電流密度、熱效應與電容寄生效應，做佈局上的改良。當其操作頻率為2.6 GHz時，其模擬結果如下，S11為-10 dB，S22為-14 dB，增益為9.2 dB，P1dB,in為14 dBm，P1dB,out為22 dBm，Psat,out為23 dBm，IIP3為 26.3 dBm，PAE為18.5%。
本論文中之電路設計是以TSMC 0.18μm CMOS 製程進行模擬，並透過CIC之申請下線，完成晶片之製作。

In this thesis, some low noise amplifiers in the front-end circuits of the radio frequency transceiver were designed, including the following circuits: a multi-mode low noise amplifier using individual switching inductors, a multi-mode low noise amplifier using stacked switching inductors, a multi-mode low noise amplifier using switching inductors and one added switching capacitor, a switchable dual-mode low noise amplifier using switching inductors and one frequency-compensation switch. Besides, in order to achieve the system integration of a front-end RF wireless transceiver and continue the research of the reliability of CMOS power cells with high output power, which had been done by graduated senior, the power amplifiers using CMOS power cells for high output power were designed.
The chip 1 is a multi-mode low noise amplifier using switching inductors. The most significant feature is using individual switching inductors to achieve three different operation modes. In mode 1, it operates with a single-band transfer characteristic (5.2 GHz); in mode 2, it operates with a dual-band transfer characteristic (2.3/5.8 GHz); in mode 3, it also operates with a dual-band transfer characteristic (2.4/5.2 GHz). When the circuit is operated in mode 1, the measured power gain is 10.4 dB and noise figure is 6.69 dB at 5.15 GHz. When it is operated in mode 2, the measured power gain is 10.5/10.3 dB and noise figure is 6.6/6.9 dB at 1.9/5.75 GHz. When it is operated in mode 3, the measured power gain is 11.3/11.3 dB and noise figure is 6.0/6.6 dB at 1.9/4.8 GHz.
The chip 2 is a multi-mode low noise amplifier using stacked switching inductors. In order to improve the drawback of large chip area in the traditional circuit architecture using individual inductors to switch operation frequency band, two inductors among three inductors of switching inductors are stacked vertically to reduce chip area. In mode 1, the circuit operates with a single-band transfer characteristic. The measured power gain is 13 dB and noise figure is 6 dB at 5.5 GHz. In mode 2, it operates with a dual-band transfer characteristic. The measured power gain is 4.7/11 dB and noise figure is 7.6/5.7 dB at 2.2/5.5 GHz. In mode 3, it also operates with a dual-band transfer characteristic. The measured power gain is 3.3/11.5 dB and noise figure is 6.9/5.9 dB at 2.1/5.7 GHz.
The chip 3 is a multi-mode low noise amplifier using switching capacitors and inductors. This chip is an extension of the chip 1 with improved performance. Adding a switching capacitor to be in parallel with the uncontrolled inductor among three inductors of the switching inductors will make the circuit apply to not only WiFi/WiMAX, but also LTE application. In mode 1, its operation mode is a dual-band mode, the measured power gain is 7.4/11 dB and noise figure is 7.5/6.1 dB at 2.0/4.9 GHz. In mode 2, its operation mode is a dual-band mode, the measured power gain is 8.1/9.2 dB and noise figure is 6.9/6.6 dB at 2.3/5.4 GHz. In mode 3, its operation mode is also a dual-band mode, the measured power gain is 11.3/9.7 dB and noise figure is 6.2/6.5 dB at 1.9/5.3 GHz. In mode 4, its operation mode is a single-band mode, the measured power gain is 11.4 dB and noise figure is 6.4 dB at 1.8 GHz.
The chip 4 is a multi-mode low noise amplifier using switching inductors and one frequency-compensation switch. The chip is an innovative architecture. The characteristics of the circuit are that it can significantly switch the operating frequency band, and it has single-band and dual-band modes while it covers almost all WiMAX frequency bands. When the circuit is operated in the single-band mode, the resonant frequency is 3.5 GHz, the simulated power gain is 11.2 dB and noise figure is 3.8 dB. When it is operated in the dual-band mode, the resonant frequency is 2.4 GHz and 5.2GHz, the simulated power gain is 16.8/16.4 and noise figure is 3.3/3.5 dB.
The chip 5 and chip 6 uses high output power cells to realize the design of power amplifier for LTE applications. The chip 5 is designed for analyzing the reliability and feasibility of the CMOS power cells with high output power when they are applied to power amplifiers, and for testing the limit of saturated output power. When the operated frequency is 2.6 GHz, the measured scattering parameters are S11 of -16 dB, S22 of -6 dB, S21 of -1.1 dB, and S12 of -29 dB. The chip has no power gain probably because the excessively large supply-feeding current IDD leads to permanent physical damage of interconnection lines for feeding current.
The chip 6 is the revised power amplifier which improves the faults of chip 5, including current density, thermal effect, and parasitic capacitance effect. When the operated frequency is 2.6 GHz, the simulated performances are as follows: the S11 of -10 dB, S22 of -14 dB, and power gain of 9.2 dB. Besides, the simulated P1dB, in, P1dB,out, Psat,out, IIP3, and PAE are 14 dBm, 22 dBm, 23 dBm, 26.3 dBm, and 18.5% respectively.
The design of these circuits is based on the TSMC 0.18μm CMOS process. These chips have been fabricated by the support of CIC in Taiwan.

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