過去的網路發展中，封包分類是一個核心課題。它可以提供像是防火牆、頻寬品質管理(QoS)、虛擬私有網路(VPNs)與網路流量控制等其他服務。然而現今網路蓬勃發展，許多新興的架構以及概念相繼被提出。其中軟體定義網路(SDN)的興起，改變了傳統的網路架構，同時對於傳統的封包分類方法也有巨大的影響。原本傳統的封包分類方法只需支援五維的規則集，軟體定義網路(SDN)則需要支援十二維、十五維或者更多維的規則集。由於規則的維度變多，相同的記憶體空間可以儲存的規則數就會變少，因此規則集的儲存問題又再度被重視。在過去，許多的多維封包分類方法都是實作於硬體FPGA上，雖然這些方法可以享受到硬體提供的高效能，但卻會受到硬體FPGA的記憶體容量所限制。
在這篇論文中，我們觀察現有的方法[22]，發現這個管線化設計的封包分類方法，沒有考慮到搜尋速度會被更新所影響。除此之外我們也發現，這個方法也沒有考慮功耗的問題。因此我們提出一個基於2-clock概念以及功耗感知的封包分類方法。2-clock概念以及功耗感知可以改善上述的問題。根據實作在Xilinx Virtex-6 XC6VLX760-2FF1760以及Xilinx Virtex-7 XC7V2000T FPGA上的實驗結果，我們的方法可以支援5K和10K以上的十二維的規則，而透過2-clock的概念，使搜尋速度能夠達到377MHz，更新速度可以達到546 MHz。除此之外，在功耗的部分，我們使用Xilinx Xpower analyzer來評估功耗，根據評估結果，我們可以使用較少的功耗來達到高效能的封包分類。

In the past network development, packet classification was an important issue. It can provide other services such as firewalls, Quality of Service (QoS), virtual private networks (VPNs) and network traffic control. However, the Internet is booming nowadays, and many new structures and concepts have been proposed one after another. Among them, the rise of software-defined networking (SDN) has changed the traditional network architecture and has a huge impact on traditional packet classification methods. The original traditional packet classification method only needs to support 5-dimensional rule set, while the software-defined network (SDN) needs to support 12-dimensional, 15-dimensional or more dimensional rule set. As the dimensions of the rules increase, the number of rules that can be stored in the same memory space will decrease. Therefore, the problem of storage of rule sets is important. In the past, many multi-dimensional packet classification methods were implemented on hardware FPGAs. Although these methods could have the high performance provided by hardware, they are limited by the memory capacity of the hardware FPGA.
In our proposed scheme, we observe the existing methods [22] and find that this pipelined design of packet classification method does not consider that the search speed will be affected by the update. In addition, we also found that this method does not consider the issue of power consumption. Therefore, we propose a power aware packet classification method based on the 2-clock concept. The 2-clock concept and power aware method can improve the above-mentioned problems. According to the experiment results implemented on Xilinx Virtex-6 XC6VLX760 and Xilinx Virtex-7 XC7V2000T FPGA, our method can support the 12-dimensional rules of 5K and 10K or more, and the 2-clock concept enables the search speed It can reach 377MHz, and the update speed can reach 546 MHz. In addition, in the part of power consumption, we use Xilinx Xpower analyzer to evaluate power consumption. According to the evaluation results, Our method has low power consumption and can achieve high-efficiency packet classification.

[1] P. Gupta and N. McKeown, “Algorithms for packet classification.” IEEE Network, vol.15, no. 2, pp.24–32, 2001.
[2] N. McKeown, T. Anderson,H.Balakrishnan, G. Parulkar, L. Peterson, J. Rexford, S. Shenker, and J. Turner, “OpenFlow: Enabling innovation in campus networks,” SIGCOMM Comput. Commun. Rev., vol. 38, no. 2, pp. 69–74, 2008.
[3] OpenFlow Foundation, “OpenFlow Switch Specification Version 1.0.0.”Available: http://www.openflowswitch.org/documents/openflow-spec-v1.0.0.pdf
[4] OpenFlow Foundation, “OpenFlow Switch Specification Version 1.1.0.”Available: http://archive.openflow.org/documents/openflow-spec-v1.1.0.pdf
[5] S. Singh, F. Baboescu, G. Varghese, and J. Wang, “Packet classification using multidimensional cutting,” in Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications (ACM SIGCOMM 2003), 2003, pp. 213–224.
[6] B. Vamanan, G. Voskuilen, and T. N. Vijaykumar. “EffiCuts: Optimizing Packet Classification for Memory and Throughput,” in Proceedings of the 2010 conference on Applications, technologies, architectures, and protocols for computer communications, 2010, pp. 207-218
[7] W. Jiang and V. K. Prasanna. “Field-split parallel architecture for high performance multi-match packet classification using FPGA.” In Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, SPAA ’09, pages 188–196, New York, NY, USA, 2009. ACM.
[8] T. Ganegedara and V. K. Prasanna, “StrideBV: Single Chip 400G+ Packet Classification.” In 13th IEEE International Conference on High Performance Switching and Routing (HPSR), 2012, pp. 1-6.
[9] F. Yu, R. H. Katz, and T. V. Lakshman, “Efficient Multi match Packet Classification and Lookup with TCAM.” IEEE Micro, vol. 25, no. 1, pp. 50-59, 2005.
[10] K. Lakshminarayanan, A. Rangarajan, and S. Venkatachary, “Algorithms for Advanced Packet Classification with Ternary CAMs.” in Proc. ACMSIGCOMM, 2005, pp. 193-204.
[11] Chang, Yeim-Kuan; Hsueh, Chun-Sheng, “Range Enhanced Packet Classification Design on FPGA.” Emerging Topics in Computing, IEEE Transactions on, 2015.
[12] P. Gupta and N. McKeown. “Packet classification on multiple fields.” In Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication, SIGCOMM ’99,pages 147–160, New York, NY, USA, 1999. ACM.
[13] H. Song and J. W. Lockwood. “Efficient packet classification for network intrusion detection using FPGA.” In Proceedings of the 2005ACM/SIGDA 13th international symposium on Field-programmable gate arrays, FPGA ’05, pages 238–245, New York, NY, USA, 2005. ACM.
[14] P. Gupta and N. McKeown. “Classifying packets with hierarchical intelligent cuttings.” Micro, IEEE, 20(1):34–41, Jan/Feb 2000.
[15] Xilinx, “Virtex-6 Family Overview” Available: http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf
[16] Xilinx, “7 Series FPGAs Overview” Available: http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf.
[17] Yun R. Qu, Shijie Zhou, and Viktor K. Prasanna, “High-performance architecture for dynamically updatable packet classification on FPGA.” Architectures for Networking and Communications Systems(ANCS), 2013.
[18] A. Basu and G. Narlikar, ”Fast Incremental Updates for Pipelined Forwarding Engines,” Proc. IEEE INFOCOM ',03, pp. ,64-74, 2003.
[19] T. Ganegedara, W. Jiang, and V. Prasanna, "Frug: A benchmark for packet forwarding in future networks," in International Performance Computing and Communications Conference Proc. IPCCC '10, IPCCC '10, 2010.
[20] W. Jiang and V. K. Prasanna, “Scalable Packet Classification on FPGA, ” IEEE Trans. VLSI Syst., vol. 20, no. 9, pp. 1668–1680, 2012.
[21] T. Ganegedara, W. Jiang, and V. K. Prasanna.“A Scalable and Modular Architecture for High-Performance Packet Classification,” IEEE Transactions on Parallel and Distributed Systems (TPDS), 2013.
[22] Chang, Yeim-Kuan “An Improved Stride-based Encoding Scheme for Packet Classification with Update”,2015.
[23] Jiří Matoušek, Gianni Antichi, Adam Lučanský, Andrew W. Moore, and Jan Kořenek, “Classbench-ng: Recasting classbench after a decade of network evolution” in Architectures for Networking and Communications Systems (ANCS), 2017 ACM/IEEE Symposium on. IEEE, pp. 204–216, 2017.
[24] Xilinx Inc. Xilinx XPower Estimator, www.xilinx.com.