在許多DSP應用中，乘法器是最關鍵的運術單元之一。這些系統的整體效能都取決於乘法器的運算能力，因此設計出一個高效能、高可靠性的乘法器是很重要的。此外，當PMOS電晶體處於負偏壓 (Vgs=-Vdd) 時，會發生負偏壓溫度不穩定性 (Negative Bias Temperature Instability, NBTI) 效應，此效應會增加PMOS電晶體的臨界電壓而降低乘法器速度。與NBTI效應相似的現象是正偏壓溫度不穩定性 (Positive Bias Temperature Instability, PBTI) 效應，此PBTI效應發生在NMOS電晶體處於正偏壓的時候。這兩種效應都會降低電晶體的速度，而電路長期受到這兩種效應影響，系統會因為時序違反(timing violations)而無法正常運作，使電路的可靠性大為降低。
在此研究裡，我們提出了一個老化感知乘法器，並使用新的自適應保持邏輯電路。這種乘法器使用可變延遲技術來提供較高的吞吐量，並能自我調整來減輕因老化效應所造成的效能衰退。此外，我們所提出的架構能應用於行旁路或列旁路乘法器。從實驗結果得知，相較於16x16和32x32固定延遲行旁路乘法器，我們提出的架構分別有62.88%和76.28%的效能提升；而與16x16和32x32固定延遲列旁路乘法器相比，我們提出的架構分別能達到80.17%和69.40%的效能提升。

Digital multipliers are one of the most critical arithmetic functional units in many DSP applications. The overall performance of these systems depends on the throughput of the multiplier. Therefore, it is important to design high-performance reliable multipliers. Meanwhile, the Negative Bias Temperature Instability (NBTI) effect occurs when a PMOS transistor is under negative bias (Vgs=-Vdd), increasing the threshold voltage of the PMOS transistor and reducing multiplier speeds. A similar phenomenon, PBTI, occurs when a NMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations.
In this work, we propose an aging-aware multiplier design with a novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and adjust itself to mitigate the performance degradation due to the aging effect. Moreover, the proposed architecture can be applied to the column- or row-bypassing multiplier. The experimental results show that our proposed architecture with the 16x16 and 32x32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement compared with the 16x16 and 32x32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with the 16x16 and 32x32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement compared with the 16x16 and 32x32 fixed-latency row-bypassing multipliers.

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