本論文首先研討應用於IEEE 802.11 a/b/g之RFIC射頻收發機系統規劃，再以TSMC 0.18m 1P6M CMOS製程來研製適用於IEEE 802.11a/b/g系統規劃之2.4/5.7 GHz CMOS雙頻WLAN收發機。第一部份之研究首先根據802.11a/b/g標準內訂定的直接降頻射頻接收機測試(靈敏度，非相鄰/相鄰頻道干擾與最大功率輸入)與參考HIPERLAN/2的阻隔測試與贅餘響應，找出符合應用於802.11a/b/g規範的直接降頻射頻接收機射頻效能參數的要求：於IEEE 802.11a規範中，NF≦10 dB，IIP3≧-20 dBm，IIP2≧-3.2 dBm，Pin,max≧-27 dBm；於IEEE 802.11b規範中，NF≦10.5 dB，IIP3≧-10.3 dBm，IIP2≧17.5 dBm，Pin,max ≧-10 dBm；於IEEE 802.11g規範中，NF≦10 dB，IIP3≧-10.3 dBm，IIP2≧17.5 dBm，Pin,max ≧-20 dBm，同時亦探討直接降頻接收機的優缺點與應用IEEE 802.11a/b/g的接收機系統規劃。
第二部份為以TSMC 0.18 m 1P6M CMOS製程來研製應用於802.11a/b/g WLAN之2.4/5.7 GHz 雙頻WLAN射頻收發機RFIC。RFIC晶片採用打鎊線至PCB上進行量測，其中包括2.4/5.7 GHz CMOS雙頻LNA、mixer、VCO、DCR及PA。最後2.4/5.7 GHz雙頻直接降頻接收模組進行整合測試，在2.4/5.7 GHz頻帶中量測所得增益為25.8/20.5 dB，雜訊指數為5.3/6.6 dB，input P1dB為-28.5/-19 dBm，IIP3為-17.5/-12.7 dBm。在數位調變訊號量測方面，於IEEE 802.11a(data rate=54 Mbps，64 QAM)訊號中，靈敏度為-71.2 dBm；於IEEE 802.11b(data rate=11 Mbps，CCK) 訊號中，靈敏度為-77.2 dBm；於IEEE 802.11g(data rate=54 Mbps，64 QAM)訊號中，靈敏度為-73 dBm。除了2.4 GHz的線性度(最大可接收功率及IIP3)低於規範外，其餘量測參數皆符合規範所需。
本論文並有研製應用於WLAN之2.4/5.7 GHz分工式CMOS雙頻超外差射頻接收機(TSMC 0.18 m)，其中整合雙頻低雜訊放大器以及混波器等電路。(列於附錄)

This thesis first presents the research on system planning for 2.4/5.7 GHz dual-band CMOS WLAN RF transceiver, and then the design and implementation of CMOS RFICs for IEEE 802.11 a/b/g WLAN RF transceiver in a TSMC 0.18 m CMOS process. In the first part, system planning parameters for direct-conversion receiver (DCR) including phase noise, noise figure, IIP3, IIP2 and I/Q imbalance are derived to meet the 802.11a//b/g standard requirements. The derived RF parameters which meet 802.11a standard requirements are: NF≦10 dB, IIP3≧-20 dBm, IIP2≧-4 dBm, input P1dB>-27 dBm; 802.11b standard requirements are: NF≦10.5 dB, IIP3≧-10.3 dBm, IIP2≧17.5 dBm, Pin,max ≧-10 dBm; 802.11g standard requirements are: NF≦10 dB, IIP3≧-10.3 dBm, IIP2≧17.5 dBm, Pin,max ≧-20 dBm. We also discuss the advantages of the direct conversion receiver and research on the system planning of the direct conversion receiver for IEEE 802.11a/b/g standard.
In the second part, the thesis presents the design and implementation of CMOS RFICs for IEEE 802.11 a/b/g WLAN RF transceiver in a TSMC 0.18 m CMOS process. The dual-band RF transceiver includes 2.4/5.7 GHz CMOS dual-band LNA, mixer, VCO, DCR and PA. For the final integrated testing, the 2.4/5.7 GHz dual-band RF receiver which includes the frequency synthesizer exhibits a conversion gain of 25.8/20.5 dB, noise figure of 5.3/6.6 dB, input P1dB of -28.5/-19 dBm, IIP3 of -17.5/-12.7 dBm. For the digital modulation measurement, the sensitivity is -71.2 dBm in the 802.11a standard (data rate = 54 Mbps, 64 QAM); the sensitivity is -77.2 dBm in the 802.11b standard (data rate = 11 Mbps, CCK); the sensitivity is -73 dBm in the 802.11g standard (data rate = 54 Mbps, 64 QAM); all of these above meet the specifications except the receiver linearity including the maximum input power and IIP3. In addition, a 2.4/5.7 GHz CMOS dual-band super-heterodyne receiver which includes dual-band LNA and mixer for WLAN applications are appendixed.

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