本論文主要分成三個部分，首先第一部份探討多相位除頻器之應用，使用TSMC 0.18-μm及90-nm CMOS製程，實現寬頻除四多相位之除頻器及K頻段之除八多相位除頻器。我們創新的利用current mode logic(CML)除頻器正交輸出特性並透過串接結構設計出具有多相位輸出之除四電路，再進一步利用多相位輸出特性搭配四次諧波混頻器設計出新穎的多相位輸出之再生式除八電路。經過量測後得到除四電路的鎖頻範圍操作於1-8.6 GHz，鎖頻範圍百分比高達133％，figure of merit(FOM)值為32.07，晶片面積為0.78 × 0.79 mm^2。除八電路的鎖頻範圍則為16.4-24.4 GHz，鎖頻範圍百分比為39.21％，FOM值則高達94.75，晶片面積為0.808 × 0.9 mm^2。
第二部份則探討正交倍頻器的應用，使用TSMC 90-nm CMOS製程，實現應用於K頻段之正交五倍頻器及77-GHz之正交九倍頻器。在五倍頻器的架構中使用了新穎的再生式電路，此再生式電路具有能夠同時除頻及倍頻的功能，並透過混頻器和三倍頻器的使用，此電路將能夠得到奇次數倍頻的作用。九倍頻器則使用了高轉換效率的正交三倍頻器，並透過耦合線來取代輸出緩衝器以節省功率消耗並同時提升輸出功率。九倍頻器的模擬結果顯示轉換增益在輸出頻率於77 GHz時為-20.69 dB，消耗功率只需4.75 mW，晶片面積為0.6 × 0.69 mm^2。
第三部份使用TSMC 90-nm CMOS製程，實現W頻段高功率耦合線之注入鎖定除頻器，本電路創新之處主要是利用耦合線達成注入訊號及輸出訊號的功能，取代傳統架構中所使用的輸出緩衝器同時節省超過百分之六十的功率消耗，並取得在W頻段下的高功率輸出。經過模擬後電路鎖頻範圍操作於79.3-82.5 GHz，直流消耗功率僅需要1.18 mW，輸出功率皆高於-6 dBm，晶片面積為0.667 × 0.407 mm^2。

Multi-phase frequency dividers, quadrature frequency multipliers, and a W-band injection-locked frequency divider for RF front-end system applications are presented. First, a novel wideband divide-by-4 multi-phase frequency divider using the quadrature output characteristic of the current mode logic and cascade technique was fabricated by the TSMC 0.18 µm CMOS process. A K-band divide-by-8 multi-phase frequency divider implemented by the TSMC 90 nm CMOS process was also achieved by combining the multi-phase frequency divider with a 4X-subharmonic mixer. The measured results of the divide-by-4 and the divide-by-8 dividers indicate that the locking range was 1 GHz to 8.6 GHz (133%) and 16.4 GHz to 24.4 GHz (39.21%), and the figure of merit was up to 32.07 and 94.75, respectively.
Second, a K-band quadrature frequency quintupler and a 77 GHz quadrature frequency multiplier-by-nine were demonstrated using the TSMC 90 nm CMOS process. An innovative regenerating circuit that can simultaneously divide and multiply the frequency was integrated with a mixer to obtain a five-time harmonic in the quintupler. In addition, the use of innovative regenerating circuit with mixer and tripler, odd frequency multipliers can be easily obtained. The implemented multiplier-by-nine was composed of a high conversion gain quadrature frequency tripler with coupled-line as the buffer stage to reduce power consumption and increase power output.
Third, a W-band high-power coupled-line injection-locked frequency divider by using the TSMC 90 nm CMOS process was also presented. The coupled-line technique was mainly used to inject the input signal and drive the next stage effectively. Compared with conventional dividers, the coupled-line technique can save over 60% of power consumption. The locking range is from 79.3 GHz to 82.5 GHz. The DC power consumption is only 1.18 mW, and the output power is higher than -6 dBm. The chip dimension is 0.667 mm × 0.407 mm.

[1] D. M. Pozar, Microwave and RF design of wireless systems, New York :JohnWiley, 2001.
[2] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[3] S. A. Mass, Microwave Mixers, 2nd ed. Boston, MA: Artech House.
[4] S. A. Maas, Nonlinear Microwave and RF circuits 2nd ed., Artech House, 2003.
[5] J. Lee, Liuyang, S. Choi, J. Lee and H. Kim, “A CMOS sub-harmonic mixer for direct conversion receiver,” in IEEE Proc. Asia-Pacific Microw. Conf., pp. 1695-1698, Dec. 2009.
[6] Ullas Singh and Michael M. Green, “High-Frequency CML Clock Dividers in 0.13-μm CMOS Operating Up to 38GHz,” IEEE J. Solid StateCircuits, vol. 40, pp. 1658-1661, Aug., 2005.
[7] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp. 1380–1385, Oct. 1973.
[8] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[9] B. R. Jackson and C. E. Saavedra, "A CMOS Ku-band 4x subharmonic mixer," IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1351-1359, June 2008.
[10] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4 injection locked frequency divider with quadrature outputs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 373-375, May 2007.
[11] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594–601, Apr. 2004.
[12] H. Zheng and H. C. Luong, “Ultra-low-voltage 20-GHz frequency dividers using transformer feedback in 0.18-μm CMOS process, ” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2293-2302, Oct. 2008.
[13] C. C. Chen, C. H. Wang, B. J. Huang, H. W. Tsao, and H. Wang, “A 24-GHz divide-by-4 injection-locked frequency divider in 0.13-μm CMOS technology,” in IEEE Proc. Asia-Pacific Microw. Conf., pp. 340-343. Nov. 2007.
[14] S. Cheng, H. Tong, J. Silva-Martinez and A. I. Karsilayan ,”A fully differential low-power divide-by-8 injection-locked frequency divider up to 18 GHz,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 583-591, Mar. 2007.
[15] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda, “20-GHz quadrature injection-locked LC dividers with enhanced locking range,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 610-618, Mar. 2008.
[16] J. C. Chien and L. H. Lu, “Analysis and design of wideband injection-locked oscillators with multiple-input injection,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1906-1915, Sep. 2007.
[17] M. W. Li, P. C. Wang, T. H. Huang and H. R. Chuang,“Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency dividers, ” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3,pp. 679-685, Mar. 2012.
[18] Q. Gu, Z. Xu, D. Huang, T. La Rocca, N. Y. Wang, W. Hant and M. C. F. Chang, “A low power V-band frequency divider with wide locking range and accurate quadrature output phases, ” IEEE J. Solid-State Circuits, vol. 43, pp.991-998, Apr. 2008.
[19] J. Lee, M. Liu, and H. Wang, " A 75-GHz phase-locked loop in 90-nm CMOS technology, " IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, June 2008.
[20] P. K. Tsai, and T. H. Huang, “ Integration of current-reused VCO and frequency tripler for 24-GHz low-power phase-locked loop applications, ”IEEE Trans. Circuits Syst. II, Exp. Briefs., vol. 59, no. 4, pp. 199-203, Apr.2012.
[21] Alan W. L. Ng, Gerry C. T. Leung, Ka-Chun Kwok, Lincoln L. K. Leung, and Howard C. Luong, “A 1-V 24-GHz 17.5-mW Phase-Locked Loop in a 0.18-μm CMOS Process, ” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 136–1244, June 2006.
[22] N. C. Kuo, J. C. Kao, Z. M. Tsai, K. Y. Lin and H. Wang, “A 60-GHz frequency tripler with gain and dynamic-range enhancement, ” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp. 660-671, May 2011.
[23] M. C. Chen, and C. Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers, ” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869-1878, Aug. 2008.
[24] W. L. Chan, and J. R. Long, "A 56–65 GHz injection-locked frequency tripler, " IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739-2746, Dec. 2008.
[25] C. N. Kuo, and T. C. Yan, “A 60 GHz injection-locked frequency tripler with spur suppression, ”IEEE Microw. Wireless Compon. Lett., vol. 20, no. 10, pp. 560-562, Oct. 2010.
[26] U. Lewark, A. Tessmann, H. Massler, A. Leuther, and I. Kallfass, “Active frequency multiplier-by-nine MMIC for millimeter-wave signal generation, ”2011 German Microwave Conference., pp. 1-4, Mar. 2011.
[27] B. R. Jackson, F. Mazzilli, and C. E. Saavedra, “ A frequency tripler using a subharmonic mixer and fundamental cancellation, ” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5,pp. 1083–1090, May 2009.
[28] You Zheng, and Carlos E. Saavedra, “A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique, ” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2197–2203, Oct. 2007.
[29] K. Yamamoto, “A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique,” IEEE J. Solid State Circuits, vol. 40, no. 6, pp. 1288–1295, Jun. 2005.
[30] D. Y. Jung and C. S. Park, “A low-power, high-suppression V-band frequency doubler in 0.13 mm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 8, pp. 551–553, Aug. 2008.
[31] M. Ferndahl, B. M. Motlagh, and H. Zirath, “40 and 60 GHz frequency doublers in 90-nm CMOS,” in IEEE MTT-S Int. Dig., vol. 1, pp. 179–182, Jun. 2004.
[32] C. S. Lin, P. S. Wu, M. C. Yeh, J. S. Fu, H.-Y. Chang, K. Y. Lin, and H. Wang, “Analysis of multiconductor coupled-line marchand baluns for miniature MMIC design,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 6, pp. 1190–1199, Jun. 2007.
[33] W. M. Fathelbab and M. B. Steer, “Tapped marchand baluns for matching applications,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp. 2543–2551, Jun. 2006.
[34] K. Tsai and S. Liu, “A 43.7 mW 96 GHz PLL in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 276–277.
[35] T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, and I. Seto, “A 60-GHz CMOS receiver front-end with frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1030–1037, Apr. 2008.
[36] Ghilioni, U. Decanis, E. Monaco, A. Mazzanti and F. Svelto, “A 6.5mW Inductorless CMOS Frequency Divider-by-4 Operating up to 70GHz," in IEEE ISSCC Dig. Tech. Paper, pp. 282-283, Feb. 2011
[37] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594–601, Apr. 2004.
[38] K.Yamamoto and M. Fujishima, “70GHz CMOS Harmonic Injection-Locked Divider,” in IEEE ISSCC Dig. Tech. Paper, pp. 600-601, Feb. 2006.
[39] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[40] Razavi, “A millimeter-wave circuit technique,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2090–2098, Sep. 2008.
[41] T. Luo and Y. Chen, “A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 620-625, Mar. 2008.
[42] Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[43] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency divider with large frequency locking range,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649–1658, Aug. 2007.
[44] Y. L. Yeh and H. Y. Chang, “Design and analysis of a W-band divide-by-three injection-locked frequency divider using second harmonic enhancement technique,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp. 1617–1625, June. 2012.
[45] Y. T. Chen, M. W. Li, T. H. Huang, and H. R. Chuang, “A V-band CMOS direct injection-locked frequency divider using forward body bias technology,” IEEE Microw. Wireless Compon. Lett., vol.20, no. 7, pp. 396–398, July. 2010.
[46] S. Verma, H. R. Rategh, and T. H. Lee, “A unified model for injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 38, pp. 1015–1027, June 2003.
[47] H. H. Hsieh and L. H. Lu, “A V-band CMOS VCO with an admittance-transforming cross-coupled pair,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1689–1696, Jun. 2009.