扇出型晶圓級封裝製程(FOWLP)具有成本低、高I/O接點數與更加的異質整合特性等優勢，因此廣泛運用於現今的封裝系統中。在製程中會經過一系列溫度循環與製程步驟，結構間的CTE不匹配會因溫差而產生翹曲，若材料選擇不當或是晶圓布局對稱性較低則容易發生非線性的翹曲，過大的翹曲則會降低產品良率。而針對此製程缺陷也有需多應用數值模擬之相關研究用以優化整體製程與材料參數組合。但大多數值模型結構詳細而複雜，若進行製程模擬有著極高的計算與時間成本。由此，本研究建立半解析模型針對非對稱翹曲的分歧點與翹曲幅度進行快速有效的預測，且在預測精準度方面半解析模型較尚未修正的解析模型精準度至多提升近兩倍，而為了更詳細觀察製程中各步驟的翹曲演變，本研究透過數值分析方法針對FOWLP中常見的chip first 與chip last製程建立製程模擬器，首先透過等效雙層結構的數值模型可在簡單的模型架構下可將各種晶圓布局與各參數的影響納入考慮，除了數值模型的有良好的泛用性之外，基於等效雙層結構模型所建立的製程模擬器在預測結果可接受的誤差範圍內得以大幅降低分析所耗費的時間，若將基於等效雙層結構模型所建的製程模擬器與以完整模型所建之製程模擬器相比，至少可節省十多倍的分析時間，最終綜合半解析模型與數值模型的預測結果根據影響翹曲的關鍵參數進行靈敏度分析，並提出翹曲防治的建議，本研究亦提出決策輔助判斷流程，透過有系統的參數探討可在新製程導入前評估各參數對於翹曲的影響力，防止大幅度的翹曲發生。綜上所述，藉由本研究所提出的製程模擬器與歸納出的關鍵參數，可對降低FOWLP製程中所產生的翹曲有所幫助，未來此研究成果也可拓展至其他封裝系統中，增進產業應用的實務價值。

Fan-out wafer level package (FOWLP) are widely used in IC packaging industry, however the asymmetric warpage in the process may affect final yield and reliability of products. Traditionally, full-scale finite element simulations are usually used for warpage and stress prediction in IC packaging, but its case-by-case nature and high computational effort are not suitable for early design stage. In this work, the semi-analytical models for predicting bifurcation and warpage are proposed as cost-effective approaches for evaluating asymmetric warping. On the other hand, for observing warpage and stress in each process step, the process emulators based on equivalent bi-layer structures FE models are developed as a quick and effective way to evaluate the effect of each factor to induce wafer warpage. To identify key parameter for reducing wafer warpage, semi-analytical models and process emulators are used for material and process parameters optimization for improving processing reliabilities. Finally, the flow of this work could also be applied to other advanced packaging process.

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