覆晶構裝(Flip chip assembly)中存在許多材料與幾何不連續之界面，這些界面可能於尖端處發生局部的應力值過大現象，因而造成破壞。本研究將對數處異相材料交接界面之位置，依照其界面型態，分別以楔形（Wedge）及全相（Junction）結構來加以模擬。文中以Muskhelishvili複變函數為理論基礎，求解多種材料楔形與全相結構之應力奇異性，探討不同材料性質與幾何外形對應力奇異性之影響。

　　首先假設所有材料性質為等向性、線彈性以及與溫度無關。固定晶片、錫球與基板的材料性質，改變底填膠之楊氏係數、蒲松氏比與角度，求得不同材料與角度組合下之應力奇異性階數。藉由應力奇異性階數─角度分佈圖，找出最小奇異性階數所對應之角度，提供覆晶構裝幾何外形與底填膠材料選擇之設計參考。

　　除了分析各界面間的應力奇異性階數外，另外針對較易破壞之晶片/錫球界面，分別探討有無底填膠時，改變一些設計參數(晶片與基板之厚度、晶片凸出距離、錫球間距、錫球幾何形狀、基板材料之楊氏係數與基板材料之熱膨脹係數)，對應力強度因子與翹曲量之影響，作為覆晶構裝可靠度之設計參考。

　In this paper, we analyze the behavior of stress singularities and obtain numerically the stress intensity factors near the geometric and material discontinuities of the flip chip assembly. The governing factors that affect the failure probability include the material properties, geometry, and the applied thermal loads. All materials are assumed to be linear elastic, isotropic and temperature independent.

　In the stress singularity analyses, we only change the material properties and assembling angles of underfill. After employing the eigenfunction expansion method on the complex potential function, the singularity orders at the wedge or junction tips in the assembly are computed numerically. From the results, the conditions for weak singularities can be obtained.

　In the second part, we focus on the determination of the stress intensity factors at chip-solder joints interface and the global warping of the integrated structure. The parameters, such as chip and substrate thickness, chip overhang, solder joints pitch, solder joint geometry, stiffness and thermal expansion coefficient of substrate, are subjected to be changed. The results provide us useful guidance for design.

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