隨著元件的微縮，增進載子遷移率來提高元件效能變得越來越重要。增進載子遷移率技術，包括混合矽基板方向技術(HOT)，淺溝槽絕緣製程(STI)應力調變和應變記憶技術(SMT)在次45奈米互補式金氧半場效電晶體元件中的應用被詳細地探討。
利用混合矽基板方向技術(HOT)和直接矽基板接合技術(DSB)，由(110)晶格方向基板直接接合(100)控制基板，能輕易地轉變傳統互補式金氧半場效電晶體成為高效率材料，特別是能在(110)晶格方向得到P型金氧半場效電晶體最高的電洞遷移率。在(110)晶格方向上，P型金氧半場效電晶體的載子遷移率和驅動電流分別被提升了2.2倍和36%。同時，P型金氧半場效電晶體的可靠度也被有系統地探討，由於較高的缺陷態位密度，負偏壓溫度不穩定性(NBTI)和時間相依介電崩潰(TDDB)都呈現顯著的衰退。在次45奈米採用混合矽基板方向技術和直接矽基板接合技術，可以大幅度的增進P型金氧半場效電晶體的效能，但仍需要考慮可靠度的問題。
一個經改善過的在次大氣壓化學氣相沉積(SACVD)所生成的淺溝槽絕緣(STI)製程被提出來增進互補式金氧半場效電晶體效能，相較於目前標準的淺溝槽絕緣製程，這個改善過的製程會產生較小的壓縮應力，這個效應可以有效地增進電子遷移率和N型金氧半場效電晶體的驅動電流；由於在<100>通道方向上較小的壓電係數，P型金氧半場效電晶體的特性將不會受到影響。隨著通道寬度及汲極/源極長度變小，這個改善過的淺溝槽絕緣製程所造成的效能增益會變的較為明顯，這是由於較小的壓縮應力。所以隨著元件面積的縮小，這個改善過的淺溝槽絕緣製程是很適用在現在以及未來更先進的製程中。
低成本應變記憶技術(SMT)被應用在40奈米的製程技術上，我們將元件成長在(100)晶格方向的基板，且利用<100>通道方向，這樣應變記憶技術對於N 型金氧半場效電晶體的驅動電流能力仍然提升了8%，同時又不會對P型金氧半場效電晶體有任何的影響。另外為了進一步探討應變記憶技術的應力儲存機制，以及應力傳導的模型，藉由改變不同的幾何結構來了解其元件特性變化，我們發現到在越小的閘極距離 (poly spacing) 與越短的源極(汲極)擴散長度 (source drain diffusion length)，其應變記憶技術改善N 型金氧元件的能力變差，也就是說應變記憶技術的應力貢獻主要是由源極(汲極)擴散區域所提供的。此外，藉由低頻雜訊量測我們發現氧化層界面品質不會受到應變記憶技術的影響，而且低頻雜訊的機制在應變記憶技術上可以適當的用單一模型來解釋。

　　Mobility enhancement to boost device performance is getting more critical as device scales. Mobility enhancement techniques, including Hybrid Orientation Technology (HOT), Shallow Trench Isolation (STI) stress modulation, and Stress Memorization Technique (SMT), were detailedly investigated for sub-45nm CMOS device applications.
　　The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for highest hole mobility. 2.2 times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) on (110) orientation were observed due to higher density of dangling bonds. To implement DSB-HOT on sub-45nm, the PMOFET performance improvement can be significantly improved but the reliability concern needs to be taken into account.
　　An improved densification process for sub-atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) was presented to enhance CMOSFET performance. The improved STI densification process will generate a lower compressive stress in the active area as compared to the Standard STI process. The reduction of STI compressive stress is beneficial to the electron mobility and leads to NMOFET drive current enhancement while no degradation on PMOSFET due to very small piezoresistance coefficients on <100> channel direction. In addition, the current enhancements will significantly increase as device dimensions (gate width and source/drain length) scales due to suppression of compressive stress. Hence, the improved STI process can be adopted in sub-40nm CMOS technology, where device structures have smaller active areas.
　　Low-cost stress memorization technique for 40nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with <100> channel orientation provides additional 8% current drivability improvement for strained-Si NMOSFETs without any degradation of PMOSFETs performance. The SMT mechanism was explored by studying the impact on layout geometry, including source/drain length (LS/D) and poly spacing. As poly spacing and LS/D of SMT device decreases, no significant current improvement is observed compared with control device, indicating that the benefit of SMT is substantially eliminated, and SMT-induced stress is mainly originated from the source/drain region. Moreover, low-frequency (1/f) noise measurements reveal that the Si/SiO2 interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1/f noise in the SMT device can be properly interpreted by the unified model.

Chapter 1
[1.1] S. M. Sze, Physics of Semiconductor Devices. New Jersey: John Wiley & Sons, 1981, pp. 91.
[1.2] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance,” IEEE Trans. Electron Devices, vol. 55, pp. 21-39, Jan. 2008.
[1.3] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. Philip Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” in Proc. of the IEEE, 2001, vol. 89, pp. 259-288.
[1.4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,” in Proc. of the IEEE, 2003, vol. 91, pp. 305-327.
[1.5] J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. R. Lin, “Band Offset Induced Threshold Variation in Strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 24, no. 9, pp. 568-570, Sep. 2003.
[1.6] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Leong, “Germanium Channel MOSFETs: Opportunities and Challenges,” IBM J. Res. and Dev., vol. 50, pp. 377-386, Jul./Sep. 2006.
[1.7] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and Mobility Characteristics of Ultra-Thin Strained Si Directly on Insulator (SSDOI) MOSFETs,” in IEDM Tech. Dig., 2003, pp. 49-52.
[1.8] M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D’Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” in IEDM Tech. Dig., 2003, pp. 18.7.1-18.7.4.
[1.9] C.-Y. Sung, H. Yin, H. Y. Ng, K. L. Saenger, V. Chan, S. W. Crowder, J. Lee, J. A. Ott, R. Bendernagel, J. J. Kempisty, V. Ku, H. K. Lee, Z. Luo, A. Madan, R. T. Mo, P. Y. Nguyen, G. Pfeiffer, M. Raccioppo, N. Rovedo, D. Sadana, J. P. de Souza, R. Zhang, Z. Ren, and C. H. Wann, “High Performance CMOS Bulk Technology Using Direct Silicon Bonding (DSB) Mixed Crystal Orientation Substrates,” in IEDM Tech. Dig., 2005, pp. 225-228.
[1.10] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative Study of Phonon-Limited Mobility of Two-Dimensional Electrons in Strained and Unstrained Si Metal Oxide Semiconductor Field-Effect Transistors,” J. Appl. Phys., vol. 80, pp. 1567-1577, Aug. 1996.
[1.11] W. Zhang, and J. G. Fossum, “On the Threshold Voltage of Strained-Si- Si1-xGex MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 263–268, Feb. 2005.
[1.12] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” in IEDM Tech. Dig., 2003, pp. 73-76.
[1.13] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key Differences for Process-Induced Uniaxial vs. Substrate-Induced Biaxial Stressed Si and Ge Channel MOSFETs,” in IEDM Tech. Dig., 2004, pp. 221-224.
[1.14] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” in IEDM Tech. Dig., 1999, pp. 827-830.
[1.15] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivkumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Trans. Electron Devices , vol. 51, pp. 1790-1797, Nov. 2004.
[1.16] T. Y. Lu, and T. S. Chao, “Mobility Enhancement in Local Strain Channel nMOSFETs by Stacked a-Si/poly-Si Gate and Capping Nitride,” IEEE Electron Device Lett., vol. 26, no. 4, pp. 267-269, Apr. 2005.
[1.17] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application,” in VLSI Symp. Tech. Dig., 2004, pp. 56-57.
[1.18] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, and M. Haond, “A Low Cost Drive Current Enhancement Technique using Shallow Trench Isolation Induced Stress for 45-nm Node,” in VLSI Symp. Tech. Dig., 2006, pp. 216-217.

Chapter 2
[2.1] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the Universality of Inversion Layer Mobility in Si MOSFET`s Part II - Effects of surface orientation,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2363-2368, Dec. 1994.
[2.2] T. Sato, Y. Takeishi, and H. Hara, “Mobility Anisotropy of Electrons in Inversion Layers on Oxidized Silicon Surface,” Phys. Rev. B Condens. Matter, vol. 4, no. 6, pp. 1950-1960, 1971
[2.3] D. Cloman, R. Bate, and J. Mize, “Mobility Anisotropy and Piezoresistance in Silicon P-type Inversion Layer,” J. Appl. Phys., vol. 39, no. 4, pp. 1923-1931, Mar. 1968.
[2.4] M. Yang, W. C. Chan, K. Chan, L. Shi, D. M. Fried, J. H. Stathis, I. Chou, E. Gusev, J. A. Ott, L. E. Burns, M. V. Fischetti, and M. Ieong, “Hybrid-Orientation Technology (HOT): Opportunities and Challenges,” IEEE Trans. Electron Devices, vol. 53, no. 5 pp. 965-978, May 2006.
[2.5] C. D. Sheraw, M. Yang, D. M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M. V. Fischetti, J. Holt, L. Black, M. Naeem, S. Panda, L. Economikos, J. Groschopf, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, D. C.-Y. Sung, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, and M. Khare, “Dual Stress Liner Enhancement in Hybrid Orientation Technology,” in VLSI Symp. Tech. Dig., 2005, pp. 12-13.
[2.6] Q. Ouyang, M. Yang, J. Holt, S. Panda, H. Chen, H. Utomo, M. Fischetti, N. Rovedo, J. Li, N. Klymko, H. Wildman, T. Kanarsky, G. Costrini, D. M. Fried, A. Bryant, J. A. Ott, M. Ieong, and C.-Y. Sung, “Investigation of CMOS Devices with Embedded SiGe Source/Drain on Hybrid Orientation Substrates,” in VLSI Symp. Tech. Dig., 2005, pp. 28-29.
[2.7] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative Study of Phonon-Limited Mobility of Two-Dimensional Electrons in Strained and Unstrained Si Metal-Oxide-Semiconductor Field-Effect Transistors,” J. Appl. Phys., vol. 80, pp. 1567-1577, Aug. 1996.
[2.8] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of Strain Effects in Semiconductors and Metal-Oxide-Semiconductor Field-Effect Transistors,” J. Appl. Phys., vol. 101, pp. 1045-1066, May 2007.
[2.9] N. Mohta, and S. E. Thompson, “Mobility Enhancement,” IEEE Circuits and Devices Magazine, vol. 21, p. 18, Sep. 2005.
[2.10] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress Engineering in Ballistic Regime,” in IEDM Tech. Dig., pp. 129-132, 2005.
[2.11] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-Plane Mobility Anisotropy and Universality under Uni-axial Strains in n- and p-MOS Inversion Layers on (100), (110), and (111) Si,” in IEDM Tech. Dig., pp. 225-228, 2004.
[2.12] S. I. Takagi, J. Koga, and A. Toriumi, “Subband Structure Engineering for Performance Enhancement of Si MOSFETs,” in IEDM Tech. Dig., pp. 219-212, 1997.
[2.13] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key Differences for Process-Induced Uniaxial vs. Substrate-Induced Biaxial Stressed Si and Ge Channel MOSFETs,” in IEDM Tech. Dig., pp. 221-224, 2004.
[2.14] L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak,O. Penzin, D. Pramanik, and K. D. Meyer, “Exploring the Limits of Stress-Enhanced Hole Mobility,” IEEE Electron Device Lett., vol. 26, no. 9, pp. 652-654, Sep. 2005.
[2.15] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate Direct Tunneling Currents in Uniaxial Stressed MOSFETs,” in Proc. of Int. EDST, p. 149, 2007.
[2.16] M. V. Fischetti et al., “Six-band k • p Calculation of the Hole Mobility in Silicon Inversion Layers: Dependence on Surface Orientation, Strain, and Silicon Thickness,” J. Appl. Phys., vol. 94, no. 2, pp. 1079-1095, Jul. 2003.
[2.17] J. Richter, Piezo Resistivity in Silicon and Strained Sioicon Germanium. Thesis, Department of Micro and Nanotechnology, Technical University of Denmark, 2004, pp. 19-41
[2.18] C. S. Smith, “Piezoresistance Effect in Germanium and Silicon,” Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.
[2.19] D. Colman, R. T. Bate, and J. P. Mize, “Mobility Anisotropy and Piezoresistance in Silicon p-type Inversion Layers,” J. Appl. Phys., vol. 39, no. 4, pp. 1923-1931, Mar. 1968.
[2.20] E. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, J. He, Z. Ma, R. Nagisetty, S. Tyagi, M. Stettler, and M. D. Giles, “Quantum Mechanical Calculation of Hole Mobility in Silicon Inversion Layers under Arbitrary Stress,” in IEDM Tech. Dig., 2004, pp. 147-150.
[2.21] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. E. Thompson, and M. Bohr, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” in IEDM Tech. Dig., San Francisco, CA, 2003, pp. 11.6.1-11.6.3.
[2.22] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, “A Novel Strain Enhanced CMOS Architecture using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films,” in IEDM Tech. Dig., Tokyo, Japan, 2004, pp. 213-216.
[2.23] M. D. Giles, M. Armstrong, C. Auth, S. M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, and K. Zawadzki, “Understanding Stress Enhanced Performance in Intel 90nm Technology,” in VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 118-119.
[2.24] C. Y.-P. Chao, and S. L. Chuang, “Spin-Orbit-Coupling Effects on the Valence-Band Structure of Strained Semiconductor Quantum Wells,” Phys. Rev. B, Condens. Matter, vol. 46, no. 7, pp. 4110-4122, Aug. 1992.
[2.25] V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen et al.,“High Speed 45nm gate Length CMOSFETs Integrated into a 90nm bulk Technology Incorporating Strain Engineering,” in IEDM Tech. Dig., San Francisco, CA, 2003, pp. 381-384.
[2.26] H. S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. C. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S. W. Crowder, B. Engel, H. Harifuchi, S. F. Huang, R. Jagannathan, E. F. Jamin, Y. Kohyama, H. Kuroda, C. W. Lai, H. K. Lee, W.-H. Lee, E. H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H. Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S.-P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I. Y. Yang, C. H. Wann, L. T. Su, M. Horstmann, Th. Feudel, A. Wei, K. Frohberg, G. Burbach, M. Gerhardt, M. Lenski, R. Stephan, K. Wieczorek, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, P. Huebler, S. Luning, R. van Bentum, G. Grasshoff, C. Schwan, E. Ehrichs, S. Goad, J. Buller, S. Krishnan, D. Greenlaw, M. Raab, and N. Kepler, “Dual Stress Liner for High Performance Sub-45nm Gate Length SOI CMOS Manufacturing,” in IEDM Tech. Dig., 2004, pp. 1075-1077.
[2.27] X. Chen, S. Fang, W. Gao, T. Dyer, Y. W. Teh, S. S. Tan, Y. Ko, C. Baiocco, A. Ajmera, J. Park, J. Kim, R. Stierstorfer, D. Chidambarrao, Z. Luo, N. Nivo, P. Nguyen, J. Yuan, S. Panda, O. Kwon, N. Edleman, T. Tjoa, J. Widodo, M. Belyansky, M. Sherony, R. Amos, H. Ng, M. Hierlemann, D. Coolbough, A, Steegen, I. Yang, J. Sudijono, T. Schiml, J. H. Ku, and C. Davis, “Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond,” in VLSI Symp. Tech. Dig., pp. 60-61, 2006.
[2.28] A. Al-Bayati, L. W. L. Q. Xia, M. Balseanu, Z. Yuan, and M. Kawaguchi,“Production Processes for Inducing Strain in CMOS Channels,” in Semiconductor Fabtech, 26th ed. London, U.K.: Bernard Henry, Trans-World House, 2004, pp. 84-88.
[2.29] P. R. Chidambaram, B. A. Smith, L. H. Hall, H. Bu, S. Chakravarthi, Y. Kim, A. V. Samoilov, A. T. Kim, P. J. Jones, R. B. Irwin, M. J. Kim, A. L. P. Rotondaro, C. F. Machala, and D. T. Grider, “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37nm Gate Length PMOS.” in VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 48-49.
[2.30] P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S.-H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr, “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnects Layers, Low-κ ILD and 0.57 μm2 SRAM Cell,” in IEDM Tech. Dig., 2004, pp. 657-660.
[2.31] M. Chu, T. Nishida, X. Lv, N. Mohta, and S. E. Thompsom, “Comparison between High-filed Piezoresistance Coefficients of Si Metal-oxide-semiconductor Field-Effect transistors and Bulk Si under Uniaxial and Biaxial Stress,” J. Appl. Phys., vol. 103, pp. 113704, 2008.

Chapter 3
[3.1] M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D’Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” in IEDM Tech. Dig., 2003, pp. 18.7.1-18.7.4.
[3.2] M. Yang, E. Gusev, M. Ieong, O. Gluschenkov, D. Boyd, K. Chan, P. Kozlowski, C. D’Emic, R. Sicina, P. Jamison, and A. Chou, “Performance Dependence of CMOS on Silicon Substrate Orientation for Ultrathin Oxynitride and HfO2 Gate Dielectrics,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 339-341, May 2004.
[3.3] L. Chang, M. Ieong, and M. Yang, “CMOS circuit performance enhancement by surface orientation optimization,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1621-1627, Oct. 2004.
[3.4] M. Yang, V. Chan, S. H. Ku, M. Ieong, L. Shi, K. K. Chan, C. S. Murthy, R. T. Mo, H. S. Yang, E. A. Lehnef, Y. Surprid, F. F. Jamin, P. Oldiges, Y. Zhang, B. N. To, J. R. Holt, S. E. Steen, M. P. Chudzik, D. M. Fried, K. Bemstein, H. Zhu, C. Y. Sung, J. A. Ott, D. C. Boyd, and N. Rovedo,“On the Integration of CMOS with Hybrid Crystal Orientations,” in VLSI Symp. Tech. Dig., 2004, pp. 160-161.
[3.5] M. Yang, K. Chan, A. Kumar, S.-H. Lo, J. Sleight, L. Chang, R. Rao, S. Bedell, A. Ray, J. Ott, J. Patel, C. D’Emic, J. Rubino, Y. Zhang, L. Shi, S. Steen, E. Sikorski, J. Newbury, R. Meyer, B. To, P. Kozlowski, W. Graham, S. Maurer, S. Medd, D. Canaperi, L. Deligianni, J. Tornello, G. Gibson, T. Dalton, M. Ieong, and G. Shahidi, “Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations,” in VLSI Symp. Tech. Dig., 2006, pp. 131-132.
[3.6] K. L. Saenger, J. P. de Souza, K. E. Fogel, J. A. Ott, A. Reznicek, C. Y. Sung, D. K. Sadana, and H. Yin, “Amorphization/Templated Recrystallization Method for Changing the Orientation of Single Crystal Silicon: An Alternative Approach to Hybrid Orientation Substrates,” Appl. Phys. Lett., vol. 87, no. 22, pp. 221911-1-221911-3, Nov. 2005.
[3.7] C. Y. Sung, H. Yin, H. Ng, K. L. Saenger, V. Chan, S. Crowder, J. Li, J. A. Ott, R. Bendernage, J. Kempisty, V. Ku, H. K. Lee, Z. J. Luo, A. Madan, R. T. Mo, P. Nguyen, G. Pfeiffer, M. Raccioppo, N. Rovedo, D. K. Sadana, J. P. de Souza, R. Zhang, Z. Ren, and C. Wann, “High Performance CMOS Bulk Technology using Direct Silicon Bond (DSB) Mixed Crystal Orientation Substrates,” in IEDM Tech. Dig., 2005, pp. 235-238.
[3.8] J. Sullivan, H. R. Kirk, S. Kang, P. J. Ong, and F. J. Henley, “Layer Transfer Process Modifications for Fabricating Hybrid Crystal Orientation Engineered Substrates,” in Proc. IEEE Int. SOI Conf., 2005, pp. 121-122.
[3.9] H. Yin, C. Y. Sung, H. Ng, K. L. Saenger, V. Chan, S. Crowder, R. Zhang, J. Li, J. A. Ott, G. Pfeiffer, R. Bendernagel, S. B. Ko, Z. Ren, X. Chen, G. Wang, J. Liu, K. Cheng, A. Mesfin, R. Kelly, V. Ku, X. J. Luo, N. Rovedo, K. Fogel, D. K. Sadana, M. Khare, and G. Shahidi, “Direct Silicon Bond (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS,” in IEDM Tech. Dig., 2006, pp. 1-4.
[3.10] H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, “Study of Wafer Orientation Dependence on Performance and Reliability of CMOS with Direct-Tunneling Gate Oxide,” in VLSI Symp. Tech. Dig., 2001, pp. 77-78.
[3.11] S. Zafar, M. Yang, E. Gusev, A. Callegari, J. Stathis, T. Ning, R. Jammy, and M. Ieong, “A Comparative Study of NBTI as A Function of Si Substrate Orientation and Gate Dielectrics (SiON and SiON/HfO2),” in Proc. IEEE VLSI-TSA Symp., 2005, pp. 128-129.
[3.12] J. S. Suehle, “Ultra-thin Gate Oxide Reliability: Physical Model, Statistics, and Characterization,” IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 958-971, Jun. 2002.

Chapter 4
[4.1] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak, and K. D. Meyer,“Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1446-1452, Jun. 2007.
[4.2] K. M. Tan, M. Zhu, W. W. Fan, M. Yang, T. Y .Liow, R. T. P. Lee,K. M. Hoe, C. H. Tung, N. Balasubramanian, G. S. Samudra, and Y. C. Yeo, “A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET,” IEEE Trans. Electron Devices, vol. 29, no. 2, pp. 1647-1656, Feb. 2008.
[4.3] G. Eneman, P. Verheyen, R. Rooyackers, F. Nouri, L. Wahington, R. Schreutelkamp, V. Moroz, L. Smith, A. D. Keersgieter, M. Jurczak, and K. D. Meyer, “Scalability of the Si1-xGex Source/Drain Technology for the 45-nm Technology Node and Beyond,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1647-1656, Jul. 2006.
[4.4] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” in IEDM Tech. Dig., 1999, pp. 827-830.
[4.5] M. Ishibashi, K. Horita, M. Sawada, M. Kitazawa, M. Igarashi, T. Kuroi, T. Eimori, K. Kobayashi, M. Inuishi, and Y. Ohji, “Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45nm Node Devices and Beyond,” Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2152-2156, 2005.
[4.6] K. Goto, Y. Tagawa, H. Ohta, H. Morioka, S. Pidin, Y. Momiyama, K. Okabe, H. Kokura, S. Inagaki, Y. Kikuchi, M. Kase, K. Hashimoto, M. Kojima, and T. Sugii, “High Performance 35nm Gate CMOSFETs with Vertical Scaling and Total Stress Control for 65nm Technology,” in VLSI Symp. Tech. Dig., 2003, pp. 49-50.
[4.7] K. Ota, T. Yokoyama, H. Kawasaki, M. Moriya, T. Kanai, S. Takahashi, T. Sanuki, E. Hasumi, T. Komoguchi, Y. Sogo, Y. Takasu, K. Eda, A. Oishi, K. Kasai, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima, T. Noguchi, and Y. Okamoto, “Stress Controlled Shallow Trench Isolation Technology to Suppress the Novel Anti-isotropic Impurity Diffusion for 45nm-Node High-Performance CMOSFETs” in VLSI Symp. Tech. Dig., 2005, pp. 138-139.
[4.8] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, and M. Haond, “A Low Cost Drive Current Enhancement Technique using Shallow Trench Isolation Induced Stress for 45-nm Node,” in VLSI Symp. Tech. Dig., 2006, pp. 216-217.
[4.9] R. Arghavani, Z. Yuan, N. Ingle, K. B. Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, “Stress Management in Sub-90-nm Transistor Architecture,” IEEE Trans. Electron Devices, vol. 51, no. 106, pp. 1740-1743, Oct. 2004.
[4.10] S. Sayama, Y. Nishida, H. Oda, T. Oishi, S. Shimizu, T. Kunikiyo, K. Sonoda, Y. Inoue, and M. Inuishi, “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less than 0.15μm Gate Length,” in IEDM Tech. Dig., 1999, pp. 657-660
[4.11] T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T. Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, and T. Nishimura, “Novel SOI Wafer Engineering using Low Stress and Hgh Mobility CMOSFET with <100>-Channel for Embedded RF/Analog Applications,” in IEDM Tech. Dig., 2002, pp. 663-666.
[4.12] H.N. Lin, H.W. Chen, C.H. Ko, C.H. Ge, H.C. Lin, T.Y. Huang and W.C. Lee, “Correlating Drain-Current with Strain-Induced Mobility in Nanoscale Strained CMOSFETs,” IEEE Electron Device Lett., vol. 27, no. 8, pp. 659-667, Aug. 2006.
[4.13] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide Induced Pattern Density and Orientation Dependent Transconductance in MOS Transistors,” in IEDM Tech. Dig., 1999, pp. 497-500.
[4.14] Y. Luo, and D. K. Nayak, “Enhancement of CMOS Performance by Process-Induced Stress,” IEEE Trans. Semi. Manufacturing, vol. 18, no. 1, pp. 63-68, Feb. 2005.
[4.15] M. H. Liao, L. Yeh, T. L. Lee, C. W. Liu, and M. S. Liang, “Superior n-MOSFET Performance by Optimal Stress Design,” IEEE Electron Device Lett., vol. 29, no. 4, pp. 402-404, Apr. 2008.
[4.16] C. Y. Hsieh, Y. T. Lin, and M. J. Chen, “Distinguishing between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 529-531, Apr. 2009.
[4.17] C. Chang, S. F. Shive, S. C. Kuehne, Y. Ma, H. Vuong, F. H. Baumann, M. Bude, E. J. Lioyd, C. S. Pai, M. A. Abdelgadir, R. Dail, C. T. Liu, K. P. Cheung, J. I. Colonell, W. Y. C. Lai, J. F. Miner, H Vaidya, R. C. Liu, and J. T. Clemens, “Enabling Shallow Trench Isolation for 0.1μm Technologies and Beyond,” in VLSI Symp. Tech. Dig., 1999, pp. 161-162.
[4.18] H. M. Chen, J. R. Hwang, Y. Li, and F. L. Yang, “Novel Strained CMOS Devices with STI Stress Buffer Layers,” in VLSI-TSA Symp., 2007, pp. 161-162.
[4.19] T. J. Wang, C. H. Ko, S. J. Chang, S. L. Wu, T. M. Kuan, and W. C. Le“The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 572-577, Feb. 2008.
[4.20] A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers, and K. Maex, “Silicide and Shallow Trench Isolation Line Width Dependent Stress Induced Junction Leakage,” in VLSI Symp. Tech. Dig., 2000, pp. 180-181.

Chapter 5
[5.1] C. W. Liu, S. Maikap, and C. Y. Yu, “Mobility-Enhancement Technologies,” IEEE Circuits Devices Mag., vol. 21, no. 3, pp. 21-36, May/Jun. 2005.
[5.2] H. C. H. Wang, Y. P. Wang, S. J. Chen, C. H. Ge, S. M. Ting, J. Y. Kung, R. L. Hwang, H. K. Chiu, L. C. Sheu, P. Y. Tsai, L. G. Yao, S. C. Chen, H. J. Tao, Y. C. Yeo, W. C. Lee, and C. Hu, “Substrate-Strained Silicon Technology: Process Integration,” in IEDM Tech. Dig., 2003, pp. 61-64.
[5.3] M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, “Strained Si, SiGe, and Ge Channels for High-Mobility Metal-Oxide-Semiconductor Field-Effect Transistors,” J. Appl. Phys., vol. 97, pp. 011101, 2005.
[5.4] S. L. Wu, Y. P. Wang, and S. J. Chang, “Controlled Misfit Dislocation Technology in Strained Silicon MOSFETs,” Semicond. Sci. Technol., vol. 21, pp. 44-47, 2006.
[5.5] Y. P. Wang, S. L. Wu, and S. J. Chang, “Tradeoff between Short Channel Effect and Mobility in Strained-Si nMOSFETs,” Semicond. Sci. Technol., vol. 22, pp. S50-S54, 2007.
[5.6] F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando, H. Ohta, K. Watanabe, and T. Onai, “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-chip Applications,” in IEDM Tech. Dig., 2000, pp. 575-578.
[5.7] A. Shimizu, K. Hachimine, N. Ohki, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” in IEDM Tech. Dig., 2001, pp. 433-436.
[5.8] T. Ueno, H. S. Rhee, S. H. Lee, H. Lee, D. S. Shin, Y. S. Jin, S. Maeda, and N. I. Lee, “Dramatically Enhanced Performance of Recessed SiGe Source-Drain PMOS by In-situ Etch and Regrowth Technique (InSERT),” in VLSI Symp. Tech. Dig., 2005, pp. 24-25.
[5.9] D. Zhang, B. Y. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shiho, A. Thean, D. Theodore, M. Canonico, S. Zollner, S. Bagchi, S. Murphy, R. Rai, J. Jiang, M. Jahanbani, R. Noble, M. Zavala, R. Cotton, D. Eades, S. Parsons, P. Montgomery, A. Martinez, B. Winstead, M. Mendicino, J. Cheek, J. Liu, P. Grudowski, N. Ranami, Tomasini, P. C. Arena, C. Werkhoven, H. Kirby, C. H. Chang, C. T. Lin, H. C. Tuan, Y. C. See, S. Venkatesan, V. Kolagunta, N. Cave, and J. Mogab, “Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement,” in VLSI Symp. Tech. Dig., 2005, pp. 26-27.
[5.10] K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,” in IEDM Tech. Dig., 2002, pp. 27-30.
[5.11] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application,” in VLSI Symp. Tech. Dig., 2004, pp. 56-57.
[5.12] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf, and F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS,” in VLSI Symp. Tech. Dig., 2006, pp. 78-79.
[5.13] G. Ghibaudo and T. Boutchacha, “Electrical Noise and RTS Fluctuations in Advanced CMOS Devices,” Microelectron. Reliab., vol. 42, no. 4/5, pp. 573-582, Apr./May 2002.
[5.14] G. Ghibaudo, O. Roux, C. Nguen-Duc, F. Balestra, and J. Brini, “Improved analysis of low frequency noise in field-effect MOS transistors,” Phys. Stat. Sol. (A), vol. 124, no. 2, pp. 571-581, Apr. 1991.
[5.15] M. P. Lu, W. C. Lee, and M. J. Chen, “Improved 1/f Noise Characteristics in Locally Strained Si CMOS using Hydrogen-Controlled Stress Liners and Embedded SiGe,” in VLSI Symp. Tech. Dig., 2006, pp. 104-105.
[5.16] Y. P. Wang, S. L. Wu, and S. J. Chang, “Low-frequency Noise Characteristics in Strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 36-38, Jan. 2007.
[5.17] H. Y. Lin, S. L. Wu, S. J. Chang, Y. P. Wang, and C. W. Kuo, “Low-frequency Noise of Strained-Si nMOSFETs Fabricated on Chemical-Mechanical -Polished SiGe Virtual Substrate,” Semicond. Sci. Technol., vol. 23, no. 10, pp. 1-4, Oct. 2008.
[5.18] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-Process -Induced Strained-Si: Extending the CMOS Roadmap,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
[5.19] A. Eiho, T. Sanuki, E. Morifuji, T. Iwamoto, G. Sudo, K. Fukasaku, K. Ota, T. Sawada, O. Fuji, H. Nii, M. Togo, K. Ohno, K. Yoshida, H. Tsuda, T. Ito, Y. Shiozaki, N. Fuji, H. Yamazaki, M. Nakazawa, S. Iwasa, S. Muramatsu, K. Nagaoka, M. Iwai, M. Ikeda, M, Saito, H. Naruse, Y. Enomoto, Kitano, S. Yamada, K. Imai, N. Nagashima, T. Kuwata, and F. Matsuoka, “Management of Power and Performance with Stress Memorization Technique for 45nm CMOS,” in VLSI Symp. Tech. Dig., 2007, pp. 218-219.
[5.20] F. Boeuf, F. Arnaud, M. T. Basso, D. Sotta, F. Wacquant, J. Rosa, N. Bicais-Lepinay, H. Bernard, J. Bustos, S. Manakli, M. Gaillardin, J. Grant, T. Skotnicki, B. Tavel, B. Duriez, M. Bidaud, P. Gouraud, C. Chaton, P. Morin, J. Todeschini, M. Jurdit, L. Pain, V. De-Jonghe, R. El-Farhane, and S. Jullian, “A Conventional 45nm CMOS Node Low-Cost Platform for General Purpose and Low Power Applications,” in IEDM Tech. Dig., 2004, pp. 425-428.
[5.21] C. Ortolland, Y. Okuno, P. Verheyen, C. Kerner, C. Stapelmann, M. Aoul aiche, N. Horiguchi, and T. Hoffmann, “Stress Memorization Technique - Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process,” IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1690-1697, Aug. 2009.
[5.22] P. Morin, C. Ortolland, E. Mastromatteo, C. Chaton, and F. Arnaud, “Mechanism of Stress Generation within a Polysilicon Gate for nMOSFET Performance Enhancement,” Mater. Sci. Eng. B, vol. 135, pp. 215-219, 2006
[5.23] A. Wei, M. Wiatr, A. Gehring, R. Boschke, C. Scott, J. Hoentschel, S. Duenkel, M. Gerhardt, T. Feudel, M. Lenski, F. Wirbeleit, R. Otterbach, R. Callahan, G. Koerner, N. Krumm, D. Greenlaw, M. Raab, and M. Horstmann, “Multiple Stress Memorization in Advanced SOI CMOS Technologies,” in VLSI Symp. Tech. Dig., 2007, pp. 216-217.
[5.24] C. M. Lai, Y. K. Fang, C. T. Lin, and W. K. Yeh, “The geometry effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2779-2785, Aug. 2006.
[5.25] G. Eneman, P. Verheyen, A. De Keersgieter, M. Jurczak, K. De Meyer, “Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1446-1453, Jun. 2007.
[5.26] A. Steegen, I. De Wolf, and K. Maex, “Local Mechanical Stress Induced Defects for Ti and Co/Ti Silicidation in Sub-0.25um MOS-Technologies,” in VLSI Symp. Tech. Dig., 1998, pp. 200-201.
[5.27] G. Eneman, M. Jurczak, P. Verheyen, T. Hoffmann, A. De Keersgieter, and K. De Meyer, “Scalability of Strained Nitride Capping Layers for Future CMOS Generations,” in Proc. ESSDERC, 2005, pp. 449-452.
[5.28] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design,” in IEDM Tech. Dig., 2000, pp. 247-450.
[5.29] P. T. Liu, C. S. Huang, P. S. Lim, D. Y. Lee, S. W. Tsao, C. C. Chen, H. J. Tao, and Y. J. Mii, “Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET,” IEEE Electron Device Lett., vol. 29, no. 11, pp. 1249-1251, Nov. 2008.
[5.30] L. K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know about 1/f Noise in MOSFETs?,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3070-3085, Nov. 2008.
[5.31] O. Marinov and M. J. Deen, “Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime” IEEE Electron Device Lett., vol. 30, no. 8, pp. 840-842, Nov. 2009.
[5.32] J. Zhuge, R. Wang, R. Huang, Y. Tian, L. Zhang, D.-W. Kim, D. Park, and Y. Wang, “Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs,” IEEE Electron Device Lett., vol. 30, no. 1, pp. 57-60, Jan. 2009.