近十年來對於無線通訊系統之研究有卓越的發展，目前對於射頻前端系統，低功率、低成本與小體積為現今無線通訊的主要訴求，為了實現以上的條件，則需先進之製程技術與創新的電路設計來互相配合。在射頻前端系統中，低雜訊放大器、混頻器與其他的被動電路為其關鍵性零組件，其中低雜訊放大器的主要目的為放大輸入端之射頻訊號，並且在射頻前端系統中，第一級之電路是用來降低來自於後級電路之雜訊，因此必須設計低雜訊放大器有著較高之增益，而高增益之低雜訊放大器將使後級的混頻器更能夠容忍較高的雜訊指數，而混頻器亦將需要較高的三階輸入截止點。另一方面，由於被動電路的尺寸正比於中心頻率之波長，因此在低頻段應用時，將需要較大之電路尺寸，而導致耗費較高的成本與需要較大之面積。而這些被動電路設計於CMOS製程時，由於CMOS基板的高頻介電損相較於其他基板製程來的高，將導致被動電路設計於CMOS製程的特性表現較其他製程差（例如，高頻PCB製程技術）。基於CMOS製程與PCB板製程的優點，本論文將探討主動電路低雜訊放大器、混頻器與被動電路其架構之設計與實現。
首先在低雜訊放大器方面，將設計應用於S頻段與C頻段之低雜訊放大器，並藉由其量測數據來探討低雜訊放大器特性表現。隨著無線通訊產業的成長，對於低雜訊放大器之特性：高增益、低雜訊指數、高線性度、低工作電壓與低消耗功率的要求相對提高，因此本論文設計一個應用於2.4-GHz的高增益低雜訊放大器，同時亦設計靜電防護電路於此電路中，與近期發表的低雜訊放大器比較，當操作在2.4-GHz頻段時，具有最低工作電壓（1-V）、最大增益（21.9-dB）與最高人體放電模式防護（±4-KV）。此外，於本論文中針對低功率損耗或高線性度之應用，亦成功設計出兩種低雜訊放大器架構分別達到這些規格。在低功率損耗應用方面，利用順向基體偏壓技術成功設計一個5-GHz頻段之低雜訊放大器，相較於近期發表之低雜訊放大器，當操作在5-GHz頻段與低工作電壓（0.6-V）時，具有較低之功率損耗（0.8-mW），並且有良好的增益（10.23-dB）與較低的雜訊指數（4.1-dB）。在高線性度應用方面，利用線性化技術成功設計一個5.5-GHz頻段之低雜訊放大器，在高頻段應用時，此線性化電路可有效地提升電路之線性度，同時不損耗低雜訊放大器之特性表現。在本論文中，亦提出一個利用LC電流合成器設計一個2.4-GHz頻段之單端帶降頻混頻器，將此混頻器與前述的高增益低雜訊放大器結合，除了可實現一個低雜訊與高增益的射頻前端接收器，另一方面亦能提升後級電路設計的彈性。
為了在射頻前端系統使用被動電路，本論文提出以高頻PCB基板製作出3-dB四分之一波長耦合器與不等量威金森功率分配器。首先，以共面波導垂直佈置耦合技術設計3-dB四分之一波長耦合器，使用此技術除了能有效地縮小耦合器尺寸，並且不需使用金屬外框來抑制不必要的電磁模態(TE and TM mode)。最後，由於不等量威金森功率分配器主要的設計與製作困難處為其需要較窄之殘段寬度，因此吾人提出利用電磁能隙共面波導(EBG CPW)技術來取代傳統的傳輸線架構，並且不需要額外的打線與背板圖形，則能有效地增加殘段寬度，並降低其設計與製作時之難度。

Wireless communications research has experienced a remarkable renaissance in the last decade. Low power, low cost, and a compact-size are the essential requirements for modern RF frond-end systems. To accomplish a successful design that meets all of these requirements, advanced process technology and circuit design techniques are necessary. In the RF frond-end system, low-noise amplifiers, mixers, and passive circuits are essential components. LNA is used to amplify RF input signals, and its gain must be kept sufficiently high to minimize the noise contributions from the following stages. Due to the high gain of LNA, the down-conversion mixer can tolerate having a higher noise figure. The mixer also requires a higher input third-order intercept point (IIP3) for the RF front-end system. Since the physical dimension of passive circuits is proportional to the wavelength of the center frequency, it drives a larger chip size and a higher cost at a low frequency application. Moreover, due to the lossy substrate of CMOS technology, the performance of passive circuits is much worse than other technologies (such as high-frequency PCB technology). Based on the advantages of CMOS and PCB technologies, the main purpose of this dissertation is to examine circuit architecture and the implementation of LNAs, mixer, and passive circuits (i.e., the 3-dB quadrature coupler and 6:1 unequal Wilkinson power divider).
In research on LNA, the design, fabrication, and measured performance of LNAs operating at the S-band and C-band will be presented. With the growth of commercial wireless systems, demands on LNA owing to its high gain, low noise figure, high linearity, low supply voltage, and low power consumption have been significantly increased. In this dissertation, a 2.4 GHz high-gain LNA with ESD protection is proposed. The fabricated LNA exhibits the lowest supply voltage (1-V) with the highest small signal gain (21.9-dB) and HBM levels (±4-KV) at 2.4 GHz as compared to recently published LNAs. To reduce power consumption or increase linearity, this dissertation will develop two LNA architectures to meet these requirements. Hence, the 5 GHz low voltage LNA using forward body bias technology is designed and demonstrated. This LNA performs relatively low-power consumption (0.8-mW) at a low supply voltage of 0.6 V, which exhibits proper gain (10.23-dB) and a lower noise figure (4.1-dB) at 5 GHz reported to date. Moreover, the 5.5 GHz LNA using the linearization technique is also proposed. The proposed linearization circuit can improve the performance of linearity for high-frequency applications while maintaining almost the same performance close to the conventional cascode LNA. Furthermore, the 2.4 GHz single-balanced down-conversion mixer with the LC current combiner was also proposed for the RF front-end receiver application. By incorporating this mixer and the previous fabricated high-gain LNA, the low-noise and high-gain RF front-end receiver is successfully demonstrated, which can improve the design flexibility of back-end stages.
To demonstrate the passive circuits for RF front-end system application, the 3 dB quadrature coupler and 6:1 unequal Wilkinson power divider are fabricated on a high-frequency PCB substrate. First, with the use of broadside-coupled coplanar waveguides technology, the 3-dB quadrature coupler can reduce the coupler size and without using an extra metallic box to inhibit spurious (TE and TM mode) propagation. Second, the EBG CPW structure is used instead of the conventional transmission line. This can eliminate the main difficulty of a narrow strip width of a 6:1 unequal Wilkinson power divider without using backside patterns and extra bonding wires.

CHAPTER 1:
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[2]T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, 1998.
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[13]A. Springer, L. Maurer, and R. Weigel, “RF System Concepts for Highly Integrated RFICs for W-CDMA Mobile Radio Terminals,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 254-267, Jan. 2001.

CHAPTER 2:
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[2]Y. Youn, N. Kim, J. Chang, Y. Lee, and H. Yu, “A 2-GHz RF Front-End Transceiver Chipset in CMOS Technology for PCS and IMT-2000 Applications,” in Digest of RFIC, pp. 271-274, May 2002.
[3]A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer”, IEEE J. Solid-State Circuits, vol. 31, pp. 1939-1996, Dec. 1996.
[4]D. K. Shaeffer, and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
[5]R. G. Meyer, and W. D. Mack, “A 1-GHz Bi CMOS RF Front-End IC”, IEEE J. Solid-State Circuits, vol. 29, pp. 350-355, March 1994.
[6]H. W. Chiu, S. S. Lu, and Y. S. Lin, “A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA With 10-mW DC Power Consumption”, IEEE Trans. Microwave Theory Tech., vol. 53, pp. 813-824, March 2005.
[7]T. Soorapanth, and T. H. Lee, ”RF Linearity of Short-Channel MOSFETs”, In First International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 81-84, July 1997.
[8]B. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE Transactions on Circuits and Systems-II, vol. 44, pp. 428-435, June 1997.
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[10]A. Springer, L. Maurer, R. Weigel, “RF System Concepts for Highly Integrated RFICs for W-CDMA Mobile Radio Terminals,” IEEE Trans. Microwave Theory Tech., vol 50, pp. 254-267, January 2001.
[11]D. Manstretta, R. Castello, F. Gatta, P. Rossi, F. Svelto, “CMOS Direct Conversion Receiver Front-End for UMTS,” IEEE ISSCC Visual Supplement, Feb. 2002, pp. 192-193.
[12]K. Kivekäs, A. Pärssinen, K. Halonen, “Characterization of IIP2 and DC-Offsets in Transconductance Mixers,” IEEE Tran. On Circuits and Systems Circuits–2, vol. 48, pp. 1028-1038, November 2001.
[13]J. Jussila, K. Halonen, “WCDMA Channel Selection Filter with high IIP2” Proceedings of ISCAS 2002, pp. I-533-I-536, May 2002.
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[15]T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, 1998.
[16]H. T. Friis, “Noise Figures of Radio Receivers,” Proceedings of the Institute of Radio Engineers, vol. 32, pp. 419–422, July 1944.
[17]M. T. Terrovitis and R. G. Meyer, “Noise in Current-Commutation CMOS Mixers,” IEEE J. Solid-State Circuits, vol. 34, pp. 772-783, Jun 1999.
[18]K. L. Fong and R. Meyer, “Monolithic RF active mixer design,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 231-239, Mar. 1999.
[19]P. J. Sullivan, B. A. Xavier, and W. H. Ku, “Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer”, IEEE J. Solid-State Circuits, vol. 32, pp. 1151-1155, July 1997.
[20]S. Wu and B. Razavi, “A 900-MHz 1.8-GHz CMOS Receiver for Dual-Band Applications,” IEEE J. Solid-State Circuits, vol. 33, pp. 2178–2185, Dec. 1998.
[21]B. Razavi, “A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs,” IEEE J. Solid-State Circuits, vol. 34, pp. 1382–1385, Oct. 1999.

CHAPTER 3:
[1]B. Razavi, “CMOS technology characterization for analog and RF design,” IEEE J. Solid-State Circuits, vol. 34, pp. 268–276, Mar. 1999.
[2]T. H. Lee, H. Samavati and H. R. Rategh, “5-GHz CMOS wireless LANs,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 268–280, Jan. 2002.
[3]W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe and S. Decoutere, “Integration of a 90 nm RF CMOS technology (200 GHz fmax - 150 GHz fT NMOS) demonstrated on a 5 GHz LNA,” IEEE Symp. VLSI Technology Dig. Tech. Papers, pp. 100–101, Jun. 2004.
[4]D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay and S. Decoutere, ” A 5-GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1434–1442, July 2005.
[5]A. Rofougaran, J. Y. C. Chang, M. Rofougaran and A. A. Abidi, “A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver,” IEEE J. Solid-State Circuits, vol. 31, pp. 880–889, July 1996.
[6]B. E. Weir. C. C. Leung, P. J. Silverman and M. A. Alam, “Gate dielectric breakdown: A focus on ESD protection,” IRPS 2004, pp. 399-404.
[7]D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May 1997.
[8]C. P. Chang, J. A. Hou, J. Su, C. W. Chen, T. S. Liou, S. C. Wong and Y. H. Wang, “A high gain and low supply voltage LNA for the direct conversion application with 4-kV HBM ESD protection in 90-nm RF CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 16, pp. 188–190, Nov. 2006.
[9]C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard, O. Prigge, C. Lin, R. Mahnkopf and B. Chen, “CMOS with active well bias for low-power and RF/analog applications,” in IEEE Symp. VLSI Circuits Tech. Dig., pp. 158–159, June 2000.
[10]D. Wu, R. Hung, W. Wong and Y. Wang, “A 0.4-V low noise amplifier using forward body bias technology for 5 GHz application,” IEEE Microw. Wireless Compon. Lett., vol. 17, pp. 543–545, July 2007.
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[12]M. N. El-Gamal, K. H. Lee and T. K. Tsang, “Very low-voltage (0.8V) CMOS receiver frontend for 5 GHz RF applications,” IEE Proc., Circuit, Devices and System, vol. 149, pp. 355–362, Oct.-Dec. 2002.
[13]Y. S. Wang, and L. H. Lu, “5.7 GHz low-power variable-gain LNA in 0.18 μm CMOS,” Electron Letters, vol. 41, pp. 66–68, Jan. 2005.
[14]H. H. Hsieh and L. H. Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Trans. Microwave Theory Tech., vol. 55, pp. 1445–1458, Mar. 2007.
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CHAPTER 4:
[1]D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay and S. Decoutere, ”A 5-GHz fully integrated ESD- protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1434-1442, July 2005.
[2]C. P. Chang, J. A. Hou, J. Su, C. W. Chen, T. S. Liou, S. C. Wong and Y. H. Wang, ”A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 16, pp.612-614, Nov. 2006.
[3]K. R. Rao, J. Wilson, and M. Ismail,”A CMOS RF front-end for a multistandard WLAN receiver,” IEEE Microw. Wireless Compon. Lett., vol. 15, pp.321-323, May. 2005.
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[5]D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS: low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May 1997.
[6]K. L. Fong and R. Meyer, “Monolithic RF active mixer design,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 231-239, Mar. 1999.
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CHAPTER 5:
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